DesignWare IP for Wearable Infotainment Applications

Overview

Wearable devices bring technology into our everyday lives by enhancing the functionality of things such as glasses, shoes, and watches that deliver real-time feedback. These devices will play a major role in the expansion of our connected world but designing SoCs that go into these devices comes with significant design challenges such as how to extend battery life, minimize area and improve sensory components (i.e. touch, voice, audio and video).

Efficient data processing will be at the heart of these solutions and Synopsys' broad DesignWare® IP portfolio is optimized to tackle these SoC design challenges. 

Mouse over or tap to learn more about DesignWare IP Solutions:

Bluetooth Low Energy

  • Link Layer and PHY
  • Operates below one volt supply
  • Integrated security functions
  • Supports the latest Bluetooth low energy standard
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Security

  • Cryptographic cores, public key accelerators, TRNG
  • Security protocol accelerators and co-processors
  • Embedded security IP modules establish secure hardware Root of Trust environments
  • Secure boot and cryptography middleware
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MIPI

  • Interoperable DSI and CSI-2 Controllers
  • Power-optimized D-PHY
  • Low-power Gear3 M-PHY
  • Compliant to standard specifications
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USB

  • USB femtoPHY cuts area by 50% - .16mm2
  • Proven USB controllers for rapid integration
  • Supports USB charge detection functionality
  • Support for power supply gating and ultra-low standby current
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LPDDR

  • DDR PHY Compiler optimizes DDR IP configuration
  • Supports auto disable of buffers, receivers & drivers to reduce power
  • Supports x16 and x32 SDRAMs
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Vision Processor

  • Delivers 1000 GOPS/W with 5x better power efficiency than GPUs
  • Programmable Convolution Neural Network object detection engine
  • High productivity programming tools with OpenCV library & OpenVX runtime and kernels
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ARC HS Processor

  • ARC HS high-performance 32-bit processors
  • >3100 DMIPS@ 1.6 GHz, 60mW power, .15mm2 area
  • Customized instructions to integrate user HW accelerators
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Data Fusion Subsystem

  • ARC EMxD for battery-operated devices requiring RISC & DSP processing
  • Data Fusion Subsystem for sensor fusion & always-on audio, voice, image processing
  • Support for tightly coupled digital and analog sensors
  • Support for tightly coupled multi-time programmable NVM
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SDIO

  • Compliant with SD 4.1, SDIO 4.1, eMMC 5.1 specifications
  • SD/eMMC supports 1-bit, 4-bit and 8-bit cards
  • Low-power option with clock & power ON/OFF features
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eMMC

  • Compliant with SD 4.1, SDIO 4.1, eMMC 5.1 specifications
  • SD/eMMC supports 1-bit, 4-bit and 8-bit cards
  • Low-power option with clock & power ON/OFF features
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SRAM

  • High-density low leakage memory w/power reduction modes
  • Ultra low voltage operation
  • Deep sleep mode reduces leakage by 70%
  • Long channel devices reduce active leakage
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ROM

  • Ultra-low power anti-signature ROM
  • Reduces leakage by up to 20%
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Logic Libraries

  • Thick oxide “always-on” libraries for static power savings
  • Multi-bit flops for dynamic power and area savings
  • Power Optimization Kit minimizes core leakage
  • Ultra low voltage operation (40% below Vddnom)
  • Learn more >>

MIPI

  • Interoperable DSI and CSI-2 Controllers
  • Power-optimized D-PHY
  • Low-power Gear3 M-PHY
  • Compliant to standard specifications
  • Learn more >>

Highlights:

  • Thick oxide "always-on" logic libraries provide the lowest leakage for always-on wakeup circuits during sleep states.
  • Ultra High Density logic libraries provide low voltage support down to 60% VddNom
  • Multi-bit flops minimize clock loading, area and leakage, improving dynamic and static power
  • Power Optimization Kits (POKs) for DesignWare Logic Libraries enable lower power consumption, while sustaining optimal performance
  • Memory compilers with advanced power management features reduce leakage by up to 70%, controlled via a single pin with 0.9V operation
  • Ultra-low power, anti-signature viaROM reduces leakage up to 20%
  • ARC HS processors deliver maximum performance efficiency (DMIPS/mW and DMIPS/mm2), ideally suited for embedded applications with high-speed data and signal processing requirements
  • Configurable and extensible instruction set of ARC HS processors enables the tailoring of each instance for optimum balance of performance, power and area
  • Programmable and configurable vision processors combine the flexibility of software solutions with the low cost and low power consumption of dedicated hardware including an object detection engine that implements convolutional neural networks
  • Sensor and Control IP Subsystem provides significant area savings with lower latency due to tightly coupled memory and sensor interface peripherals as well as hardware accelerators to improve performance & reduce code size
  • DDR multiPHY IP combined with DesignWare Universal DDR digital controller and verification IP provides a complete multi-protocol DDR interface IP solution supporting LPDDR2/3
  • MIPI CSI-2 and DSI controllers are compliant to specifications rev 1.2. Support 1 to 8 and 1 to 4 data lanes respectively with D-PHY PPI interface operating up to 2.5 Gbps per lane
  • ADCs with up to 14-bit resolution and 5 Msps conversion rates exceed leading on-chip implementations
  • Proven, certified USB 2.0 controllers and PHYs are easy to integrate and support Battery Charging with low-power features
  • Compact Bluetooth low energy Link Layer and PHYs enable secure wireless connectivity with extended reach, and low power consumption for extended battery life targeting wearables and smart home applications
  • Security IP including Public Key Accelerators, True Random Number Generators and security protocol accelerators and secure hardware root of trust protects against evolving threats