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The Synopsys Ethernet MAC IP enables the host to communicate data using the Ethernet protocol (IEEE 802.3) at 10 or 100 Mbps speeds. The IP is composed of three main layers: the Media Access Controller (MAC), the MAC Transaction Layer (MTL), and the MAC DMA Controller (MDC). Silicon-proven and designed for easy integration into ASICs and FPGAs, the Synopsys Ethernet MC IP comes with a user-friendly application interface so that designers can easily set their functional and implementation objectives to meet design requirements. The IP is verified using state of the art methodologies to reduce risk. The deliverables include the RTL design, verification, hardware verification, and interoperability tests.

 

The Synopsys Ethernet IP solutions consist of configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.

 

Highlights & Key Features

Highlights
Highlights + -

  • General Features
    • Compliant with IEEE 802.3-2008 specifications for 10M/100M Ethernet
    • Supports IEEE 802.1Q VLAN tag detection for reception frames
    • Supports CSMA/CD protocol for half-duplex operation
    • Supports full-duplex only configuration
    • Supports back pressure for flow control in half-duplex mode and 802.3x flow control in full-duplex mode
    • Supports configurable number of RMON statistics counters
    • Supports power management using magic Packet and Wake-up frames
    • Flexible and wide range of address filtering schemes
    • TCP/IP Checksum offload engines in TX and RX paths
    • Supports basic IEEE 1588 time stamping
  • PHY Interface Features
    • Media Independent Interface (MII)
    • Reduced MII (RMII)
    • Serial MII (SMII)
    • Reverse MII (RevMII)
  • Application Interface Features
    • Fully synchronous design operating on a single system clock
    • 32/64/128-bit data transfers and Little-Endian and/or Big-Endian operation
    • Individual programmable burst size for Transmit and Receive DMA Engines
    • Descriptor architecture allowing large blocks of data transfer with minimum CPU intervention & comprehensive status reporting for normal operation and transfers with errors
    • Programmable interrupt options for different operational conditions
    • Provides separate ports for host CSR and host DATA access
    • CSR access interface configurable for APB, AHB or native interface
    • Data access interface configurable for FIFO (without DMA), AHB, or native interfaces
    • AHB device Interface supports all AHB Burst types
    • Software selectable AHB burst type (Fixed or unspecified) on AHB Manager interface

    • Product Details

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