EDA
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IP
SolvNetPlus
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The DWC_xpcs core is designed to support the following derivatives of the PCS layer:
- XAUI
- RXAUI
- 1000BASE-X or SGMII
- 10GBASE-X
- 10GBASE-R
- 10GBASE-KX4, 10GBASE-KR, 1000BASE-KX
The Synopsys Ethernet PCS IP is verified using state-of-the-art methodologies including the RTL design, verification, hardware verification and interoperability tests. The IP is easily configured with a user-friendly application interface for easy functional and implementation objectives to meet design requirements, making the Synopsys Ethernet PCS IP a streamlined and flexible solution. Coupled with the Synopsys XGMAC IP and a configurable MAC that supports 1G/2.5G/5G/10G Ethernet applications, the Ethernet PCS IP offers easy SoC integration into 1G/2.5G/5G/10G Ethernet designs.
The Synopsys Ethernet IP solutions consist of configurable Controllers and silicon-proven PHYs supporting speeds of up to 100G, MACsec Security Modules, Verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.
Highlights & Key Features
- Compliant with IEEE 802.3ae Clause 47 and Clause 48 for XGXS applications and IEEE 802.3ap Clause 36, Clause 45, Clause 48 and Clause 73 for 1000B-KX, 10GBASE-KX4, auto negotiation and consortium specifications
- Supports Clause 37 auto negotiation for 1000BASE-X applications
- Compliant with Clause 36 and Clause 37 auto negotiation for 1000BASE-X applications
- Easily configurable for 10 Gigabit Ethernet applications using XGXS-PCS or 10GBASE-X PCS and/or Gigabit application like 1000BASE-X
- Option to support Industry standards like RXAUI and SGMII (10/100/1000 Mbps operating modes)
- Backplane Ethernet for KX and KX4, KX only or KX4 only with KX configurations capable of 2.5 Gigabit Ethernet speeds simply by increasing the clock frequency
- Conversion of dual data rate XGMII to single data rate 312.5 MHz data-bus
- Optional conversion of double data width (64 bit) XGMII operation with 156.25 MHz clock to single data rate (32-bit) operating with 312.5 MHz clock
- Seamlessly integrates with the Synopsys XAUI-PHY SerDes
- Option to have either IEEE 802.3 Clause 45 compliant MDIO serial interface or parallel micro-controller interface for the host.
- Conversion of XGMII idle control characters to a randomized sequence of code groups to enable lane synchronization, land to lane alignment and clock rate compensation
- 8B/10B encoding to convert the binary data to 10-bit encoded data for each lane
- Lane synchronization on receive side to determine code-group boundaries
- De-skew of all received code groups to an alignment pattern with a maximum allowed skew over 5 cycles
- Clock rate compensation in which idle characters are inserted or deleted to compensate for the frequency variations between the recovered clock and the local clock with a maximum allowed variation between the clocks of 200ppm
- Supports internal loop-back on the XGMII for debugging through receive to transmit digital path and loopback control of the SerDes PHY transmit to SerDes PHY receive lane
- Link status reporting for faulty conditions and multiple options for error status and statistics available for monitoring and debugging
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