DVCon US 2021

March 1-4, 2021
Virtual Experience 

 

Why Attend?

Synopsys is the world’s leading provider of solutions for designing and verifying advanced silicon chips. Visit us at DVCon US 2021 to learn how we help customers optimize chips for power, performance, and cost and cut months off their project schedules. 

Join Synopsys' Tutorial

Raising The [Verification] Bar: Cloud-Based Simulation Increases Verification Efficiency
Date: Thursday, March 4th 
Time: 9:00 a.m. – 11:00 a.m. PST

In this tutorial, architects from AWS, verification experts from Synopsys, and customers running simulation on the cloud will discuss these challenges and demonstrate a software development kit (SDK) including all the scripts required to setup a complete verification environment on the AWS. A joint solution between AWS and Synopsys has been developed to help customers bring their verification environments to AWS. 


Visit Synopsys' Virtual Booth 

Stop by to see how we deliver comprehensive verification solutions spanning the complete design cycle, including simulation, emulation, advanced debug, static/formal verification, FPGA-based prototyping and virtual prototyping. 

Virtual Exhibit Hours:
Tuesday, March 2            2:00 p.m. - 5:00 p.m. PST
Wednesday, March 3      2:00 p.m. - 5:00 p.m. PST
Thursday, March 4         12:30 p.m. - 1:30 p.m. PST

 

Sponsored Engagement

Title: Advanced Integrated Development Environment for SoC Design and Verification

Date: Tuesday, March 2nd

Time: 2:00 p.m. - 2:30 p.m. PST

Abstract: Two things are certain in chip design and verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. This presentation will highlight the need for an innovative solution and bring the best practices of software development to hardware design and verification with customer case studies from DeepAI and Quantum Machines.

 

Title: Datapath Validation Using Formal Techniques

Date: Tuesday, March 2nd

Time: 4:00 p.m. - 4:30 p.m. PST

Abstract: CPU, GPU and AI designs are datapath heavy with unique design characteristics and require advanced verification techniques and methodology. These designs have mathematical functions like addition, subtraction, multiplier, square root, and floating-point units (FPU). Verifying these mathematical functions using traditional methods is inefficient, time consuming and impractical. This presentation will highlight the need for an innovative datapath validation solution and share best practices through customer case studies from Samsung and Intel.

 

Title: The New Power Perspective – Realistic Workloads – Real Results

Date: Wednesday, March 3rd

Time: 2:00 p.m. - 2:30 p.m. PST

Abstract: Have you ever gone through the huge effort of taping out your next-generation SoC only to find out when it’s too late that your design is drawing 30% more power?  Your team was likely disappointed after pushing hard to reduce power by a small percentage, only to realize that the goal was missed by much more.

In this session we will explain why this still happens. We will explore a whole new perspective of possibility for power profiling SoC designs. You will learn about breakthrough emulation technology that enables multiple iterations per day with actionable results in the context of the full SoC design and its software workload. The power profiles can be used by software and hardware designers to identify substantial power improvement opportunities helping to ensure that power targets are met.

 

Title: Advanced Integrated Development Environment for SoC Design and Verification

Date: Wednesday, March 3rd

Time: 5:00 p.m. - 5:30 p.m. PST

Abstract: Two things are certain in chip design and verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. This presentation will highlight the need for an innovative solution and bring the best practices of software development to hardware design and verification with customer case studies from DeepAI and Quantum Machines.