If you're involved with system validation or hardware/software integration tasks then you're painfully aware of the demanding prototype project schedule that drives engineers to deliver operational prototypes within weeks or even days following the RTL "drop" from the design and verification team. There is little time for delay and this focus on reducing the "time-to-first" prototype has influenced the design and usage model for the HAPS design environment, HAPS ProtoCompiler.
HAPS ProtoCompiler delivers key features and benefits to address both rapid prototype bring-up and fast system performance:
- Parallel processing, runtime optimizations, and short design iteration loops allow designers to deliver an operational HAPS system within days of RTL/IP availability
- Billion ASIC gate capacity to handle the highest-capacity HAPS Series systems ensures that you can support SoC/ASIC prototype projects today and in the future
- Constraint-driven partitioning, high-speed time-domain multiplexing of FPGA I/Os, and system-level routing to maximize HAPS system clock performance
- Flexible and high-capacity debug storage options for single or multi-FPGA debug maximizes visibility and sample rates available for HAPS systems
- ARM AMBA compatible transactor-level interfaces ease implementation of hybrid prototypes
For more information on Synopsys physical prototyping software tools for custom-built ASIC prototypes, see Synplify Premier.