An Overview of Synopsys HAPS Prototyping Software

Maximizing Productivity with Synopsys Prototyping Software

Synopsys’ prototyping software tools provide engineers with design planning, logic synthesis, and debug, tools to address the largest system-on-chip (SoC) designs. Synopsys prototyping software is applied by hundreds of design teams worldwide to maximize productivity when using HAPS systems.

System validation or software development teams care about one thing: how quickly can they get all their development and validations tasks done, when they receive the prototype from the prototyping team. Their key concern is the performance of the prototype. Some software teams will refuse to touch the prototype and wait for silicon.

Optimizing Prototype Performance with HAPS Prototyping Software

HAPS prototyping software helps the prototyping team to take a design and create the fastest performing implementation on the HAPS prototyping hardware. It does so by enabling the prototype to find both the optimum partitioning between the FPGAs and the best connectivity using the HapsTrak3 cable. After this is done the HAPS prototyping software will use its proven timing-driven synthesis engine to create the optimum prototype. It will handle complicated clocking structures and map them into a performance to optimized prototype.

Key Features of HAPS ProtoCompiler for Rapid Prototype Bring-up and System Performance

HAPS ProtoCompiler delivers key features and benefits to address both rapid prototype bring-up and fast system performance:

• Parallel processing, runtime optimizations, and short design iteration loops allow designers to deliver an operational HAPS system within days of IP/RTL source code availability.
• Billion ASIC gate capacity to handle the highest-capacity HAPS systems ensures that you can support SoC/ASIC prototype projects today and in the future.
• Constraint-driven partitioning, high-speed time-domain multiplexing of FPGA I/Os, and system-level routing to maximize HAPS system clock performance.
• Flexible and high-capacity storage options for single or multi-FPGA debug maximizes observability and sample rates available for HAPS systems.
• Arm AMBA compatible transactor level interfaces ease implementation of hybrid prototypes.

Unified Debug Approach for System Level Validation and Prototype Bring-up

For system level validation and prototype bring-up prototyping teams rely on the industry standard Verdi debug solution including proven data expansion from the captured debug state information, name correlation from the HAPS prototype image to the RTL design source data and the familiar waveform debug that enables RTL verification engineers and prototypers to jointly look the design and root cause errors quickly. This unified debug approach saves valuable time for the overall project schedule.