Synopsys’ HAPS prototyping systems are used when synthesizable RTL source code of the ASIC/system-on-chip design is available, allowing designers to develop software, verify SoC hardware and enable system validation before the silicon is taped-out. Hardware and software design teams can deploy HAPS® systems in a variety of roles in the SoC development cycle.
HAPS prototypes deliver multi-megahertz operation to help speed the verification of IP and subsystems that require high-volumes of test patterns to confirm operation. There are two popular use models, one with memory pre-load/readback of HapsTrak 3 memory daughter boards or direct streaming from the host workstation. The HAPS UMRBus supports both scenarios with a stable and high-performance physical link and APIs to ease integration between a host workstation and a HAPS system via a USB or PCIe connection. For DUT testing, preload and readback of on-board DDR3 SDRAM with test and result data is ideal for review of media codecs. The Synopsys SolvNet Catalog of HAPS Design Examples includes DUT test jigs that integrate DDR3 memory interface controller for the HapsTrak 3 8 GB memory module. The UMRBus API for Tcl/C/C++ makes adoption into your test environment easy and HAPS’ superior modularity and reusability allows you to focus on new design and verification tasks instead of developing custom test equipment.
By using a high-performance prototype, software development can begin much sooner in the design process. A HAPS system can achieve internal system frequencies in 100s of megahertz, making it feasible for SoC designs to execute the low-level firmware of the software stack, as well as the full operating system and even applications. When coupled with a Virtualizer™ virtual prototype, HAPS prototypes run concurrently with SystemC/TLM-based processor models, creating a unique and powerful hybrid prototype that delivers the best of both prototyping methods.
HAPS systems are light and portable. They can be powered with conventional power sources and quickly assembled in the field for customer demonstrations, industry conferences, “plug-fests”, and validation scenarios outside of the lab environment.
ASIC prototypes are now often integrated as a shared IT resource. In order to maximize the ROI and regression throughput HAPS-80 prototyping incorporates sharing and management features to support both multi-design and remote shared usage scenarios. HAPS Multi-Design Mode (MDM) features allow multiple independent designs to be programmed onto a multi-FPGA HAPS system. This helps HAPS users to avoid idle FPGAs and maximize utilization of multi-FPGA systems and a more parallel work flow. Integrated Ethernet interface and a runtime management server allow remote clients to attach to the system to assign and run designs to one or more FPGAs. This allows runtime scenarios for individual IP blocks, subsystems, or full SoC designs to be run concurrently.