Systemverilog Assertions

Overview

In this intensive, one-day course, you will learn the key features and benefits of the SystemVerilog Assertion language and its use in VCS.

This course is a hands-on workshop that reinforces the verification concepts taught in lecture through a series of labs. At the end of this workshop, students should have the skills required to write SystemVerilog Assertions to verify a device under test using VCS. Students will also learn how to use assertion libraries and obtain coverage information on assertions.

Students will first learn how to write immediate and concurrent assertions. Next the workshop will explain in-depth the use of sequences to write assertions and make them reusable and scalable. The course then discusses assertion coverage and use of cover properties that allows you to assess the effectiveness and efficacy of your testbench. Lastly the course introduces you to the application of assertion libraries shipped with VCS to capture standard behaviors in a scalable, reusable form.

To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design. Students are expected to have completed the three-day System Verilog Testbench workshop offered by Synopsys.

Objectives

At the end of this workshop the student should be able to:

  • Create Immediate and Concurrent assertions
  • Use reusable properties and sequences in assertions
  • Use different methods of embedding assertions in a testbench
  • Bind assertion modules to the components of a testbench
  • Debug assertion output using DVE
  • Use cover properties in a testbench
  • Use assertion libraries in a testbench
  • Measure coverage on assertions and cover properties

Audience Profile

Design or Verification engineers who need to write assertions

Prerequisites

To benefit the most from the material presented in this workshop, you should have:

  • Completed the three-day System Verilog Testbench course offered by Synopsys
  • An understanding of basic concepts of design verification
  • Working knowledge of SystemVerilog
  • Experience with a high-level programming language (such as C)
  • Familiarity with UNIX workstations running X-windows
  • Familiarity with vi, emacs or other UNIX text editor

Course Outline

  • Introduction to Assertions
  • Immediate and Concurrent Assertions
  • Sequences
  • Assertion Coverage
  • Assertion Libraries

Synopsys Tools Used

  • VCS 2017.03
  • VERDI 2017.03