Power-Aware Verification with VCS-NLP and UPF


In this intensive, one-day course, students will learn the key features and benefits of using VCS-NLP to perform power-aware functional simulations.

This course is a hands-on workshop that reinforces the power-aware verification concepts taught in lecture through a series of labs. At the end of this workshop, students should have the skills required to use a power intent defined in UPF to run functional simulations using VCS-NLP to verify the effect of the power intent on the correct functioning of their design.

Students will first learn how to define basic power intent using UPF. Then they will understand the impact of simulating this power intent by running simulations using VCS-NLP. Next the workshop will explain how to debug the simulations using power-aware Verdi3. They will also learn how to control certain behavior of the simulation to investigate potential problems with the design with respect to the power intent. This course continues with a discussion of automation and control functional coverage that allow you to assess the percentage of functionality covered in power-aware simulation, both dynamically and through the use of generated reports. Finally, as an additional benefit, students will also see the use of static checks to further verify power intent.

To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.


At the end of this workshop the student should be able to:

  • Understand the impact of power on designs
  • Define use and control of power domains in a power-aware simulation
  • Define basic UPF policies of power domains
  • Understand power objects associated with a power domain
  • Run power-aware RTL simulation using VCS-NLP and UPF
  • Debug the output of power-aware RTL simulation using Verdi3
  • Understand the control of power-aware simulation using UPF attributes
  • Understand the reports generated by VCS to instrument the RTL for power-aware simulation
  • Understand the assertions reported by VCS during a power-aware simulation
  • Report coverage on a power-aware simulation using VCS
  • Get a basic understanding of static checks using VC LP for power-aware design flow

Audience Profile

Design or Verification engineers who write power-aware testbenches at the block or chip level


To benefit the most from the material presented in this workshop, students should have:

  • A basic understanding of digital IC design
  • A basic understanding of Verilog HDL and simulation using Testbenches
  • A basic understanding of SystemVerilog interfaces
  • Familiarity with UNIX workstations running X-windows
  • Familiarity with vi, emacs, or other UNIX text editors
  • Familiarity with Tcl

Course Outline

Day 1

  • Introduction to Low Power
  • Power Intent and UPF
  • Power-Aware Simulations using VCS
  • Debugging Power-Aware Simulations
  • Power-Aware Simulation Coverage
  • Introduction to VC LP Static Checks

Synopsys Tools Used

  • VCS 2016.06-SP2
  • VERDI 2016.06-SP2
  • VC STATIC 2016.06-SP2