SystemVerilog for RTL Design

Overview

In this hands-on workshop, you will learn how to develop RTL coding using SystemVerilog. You will apply SystemVerilog constructs in your RTL code to prevent synthesis/simulation mismatches. You will write RTL code which avoids unintentional combinatorial logic and latches. You will use SystemVerilog interface mechanism to simplify module connectivity. You will develop proper synthesis scripts to manage parameters in RTL code for reuse in RTL block level integration and gate-level simulation.
 

Objectives

At the end of this workshop the student should be able to:

  • Use always_comb, always_latch and always_ff to get intended combinatorial, latch and register logic
  • Use typedef enum to create self-documenting state machine code
  • Use packed struct and interface to simplify module connectivity
  • Learn DC TCL scripting to support parameterized module and interface
  • Learn how shared resources and duplicated resources impact QoR for area and timing
  • Learn how to use DesignWare logic in RTL code
  • Learn the basics of DC optimization

Audience Profile

Design or Verification engineers who need to understand SystemVerilog for RTL design.
 

Prerequisites

To benefit the most from the material presented in this workshop, students should have a good understanding of the Verilog language.
 

Course Outline

Verilog & Synthesis Review
  • Verilog review
  • Synthesis view of Verilog code
  • Synthesis flow
Basic SystemVerilog Features
  • SystemVerilog data types
  • SystemVerilog operators
  • SystemVerilog functional blocks
  • SystemVerilog module
Implementing User Logic Intent
  • Understanding issues with the Verilog always statement
  • Avoiding unintentional latch
  • Understanding the meaning of full and parallel during synthesis
  • Applying priority and unique to avoid synthesis/simulation mismatch
  • Dealing with wildcards
  • Implementing registers with synchronous and asynchronous set and reset
  • Implementing tri-state logic
  • Using enum data type for self-documenting state machine code
Advanced SystemVerilog Features
  • Packed/unpacked array
  • Packed/unpacked struct and union
  • interface
  • modport
  • Parameterized module
  • Parameterized interface
  • Parameterized function
Achieving High QoR - Coding
  • Readability
  • Impact of different coding styles
  • Embedding DesignWare logic in RTL code
  • Efficiencies of case vs. for loop
  • Achieving both area and timing QoR in for loop
  • Catching datapath leakage in RTL code
Achieving High QoR - DC optimization
  • Resource sharing
  • Resource recording
  • Adaptive re-timing
     
Synopsys Tools Used
  • DC 2016.12
  • VCS 2016.06