Design Compiler: RTL Synthesis


This course covers the RTL synthesis flow: Using Design Compiler in Topographical mode to synthesize a block-level RTL design to generate a gate-level netlist with acceptable post-placement timing and congestion. You will learn how to: Read in hierarchical block-level RTL designs; Load libraries, technology data and floorplan constraints; Apply and verify constraints for complex design timing; Use timing- and congestion-focused DC Ultra and DC Graphical optimization features, which includes the SPG flow, to achieve post-placement timing closure and acceptable congestion; Analyze synthesis results for timing and congestion; Generate output data required by physical design or layout tools.

The course includes labs to reinforce and practice key topics discussed in lecture. Optionally, you will verify the logic equivalence of synthesis transformations (such as datapath optimizations and register retiming) to that of an RTL design using Formality.

All the covered commands and flows are printed separately on an 8-page “Job Aid” hand-out, which the student can refer to back at work.



At the end of this workshop the student should be able to:

  • Load the logic libraries, as well as physical technology and design data which are required for synthesis in DC Topographical mode
  • Read in hierarchical RTL designs
  • Constrain a complex design for timing (includes: ideal clock modeling using master, virtual and generated clocks; input and output port constraints; modeling mutually-exclusive, asynchronous and multi-cycle clocks)
  • Apply DC Ultra techniques to achieve timing closure with good post-layout correlation
    (includes: auto-ungrouping, boundary optimization, test-ready synthesis, adaptive and register retiming, prioritizing and enabling high-effort timing optimization, path groups, TNS-driven placement)
  • Take advantage of DC-Graphical features to improve timing closure, reduce congestion, and improve post-placement timing correlation (includes: register duplication, net layer optimization, netlist topology optimization and physical guidance to ICC or ICC II)
  • Generate and interpret timing and constraint reports
  • Analyze global route-based congestion
  • Generate output data (netlist, constraints, scan-def, coarse placement) that is needed to implement the layout (place and route)
  • Write DC-Tcl scripts to constrain designs, and run synthesis


Audience Profile

ASIC digital designers who need to use Design Compiler to synthesize RTL designs to gates.


Prior experience with Design Compiler is not needed. An understanding of basic digital ASIC design concepts is assumed, including combinational and sequential logic functionality, and setup and hold timing. The ability to work in a Unix/X-windows environment, using a text editor such as emacs, vi, pine, is required for labs. 

Course Outline

Day 1

  • Introduction to Synthesis
  • Data Setup for DC Topographical Mode
  • Accessing Design and Library Objects
  • Constraints: Reg-to-Reg and I/O Timing

Day 2

  • Constraints: Reg-to-Reg and I/O Timing
  • Constraints: Input Transition and Output Loading
  • DC Ultra Synthesis Techniques 

Day 3

  • Timing Analysis
  • Constraints: Multiple Clocks and Exceptions
  • DC Graphical: SPG Flow, Congestion, Layout GUI
  • Constraints: Complex Design Considerations
  • Post-Synthesis Output Data
  • Conclusion


Synopsys Tools Used

  • Design Compiler 2017.09-SP4
  • Formality 2017.09-SP4