RTL Synthesis

Design Compiler: RTL Synthesis

This course covers the RTL synthesis flow using Design Compiler to generate a gate-level netlist with acceptable post-placement timing and congestion.

Design Compiler: Low Power

This seminar based course covers Low Power Synthesis using Design Compiler Topographical with Power Compiler by using traditional (single voltage) and UPF based (multi voltage, multi supply) power optimization techniques.

DFT Compiler

In this course you will learn to use DFT Compiler to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and insert scan using top-down and bottom-up flows.

SpyGlass DFT ADV

In this course you will learn how to run SpyGlass DFT ADV to perform RTL and gate-level testability checks, analyze hard to test areas and explore adding test points to improve coverage and QOR. You will also be introduced to using connectivity checks to verify block and SoC level connections.

SystemVerilog for RTL Design

In this course, you will learn how to achieve high quality of results for your RTL design using SystemVerilog. It is assumed that you are versed in Verilog and want to improve your RTL coding efficiency with SystemVerilog.