This course covers the RTL synthesis flow: Using Design Compiler NXT in Topographical mode to synthesize a block-level RTL design to generate a gate-level netlist with acceptable post-placement timing and congestion.
Learn to use Fusion Compiler to perform physical synthesis using the compile_fusion command, which unifies traditional synthesis with placement and optimization, along with additional physical design techniques such as concurrent clock and data optimization.
In this course, you will learn how to achieve high quality of results for your RTL design using SystemVerilog. It is assumed that you are versed in Verilog and want to improve your RTL coding efficiency with SystemVerilog.
In this workshop, you will learn to use TestMAX Advisor (previously known as SpyGlass DFT) to perform RTL testability analysis that will allow you to fine-tune your RTL early in the design cycle. This will verify the design scan readiness and Test Robustness and work towards meeting fault and test coverage goals.