RTL Synthesis

Design Compiler NXT: RTL Synthesis

This course covers the RTL synthesis flow: Using Design Compiler NXT in Topographical mode to synthesize a block-level RTL design to generate a gate-level netlist with acceptable post-placement timing and congestion.

Fusion Compiler Synthesis

Learn to use Fusion Compiler to perform physical synthesis using the compile_fusion command, which unifies traditional synthesis with placement and optimization, along with additional physical design techniques such as concurrent clock and data optimization.

Fusion Compiler Synthesis Jumpstart eLearning

This jumpstart will give you an overview of Fusion Compiler frontend features and flow, especially around the compile_fusion command which performs RTL synthesis and placement optimization.

SystemVerilog for RTL Design

In this course, you will learn how to achieve high quality of results for your RTL design using SystemVerilog. It is assumed that you are versed in Verilog and want to improve your RTL coding efficiency with SystemVerilog.

TestMAX Advisor (SpyGlass DFT)

In this workshop, you will learn to use TestMAX Advisor (previously known as SpyGlass DFT) to perform RTL testability analysis that will allow you to fine-tune your RTL early in the design cycle. This will verify the design scan readiness and Test Robustness and work towards meeting fault and test coverage goals.


In this course you will learn to use TestMAX DFT to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and insert scan using top-down and bottom-up flows.

Timing Constraints for Synthesis eLearning

This course covers SDC timing constraints for synthesis, focused on setup timing, applicable to Design Compiler, Design Compiler NXT or Fusion Compiler.