RTL Synthesis

Design Compiler: Low Power

This seminar based course covers Low Power Synthesis using Design Compiler Topographical with Power Compiler by using traditional (single voltage) and UPF based (multi voltage, multi supply) power optimization techniques.

Design Compiler: RTL Synthesis

This course covers the RTL synthesis flow using Design Compiler to generate a gate-level netlist with acceptable post-placement timing and congestion.

DFT Compiler

In this course you will learn to use DFT Compiler to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and insert scan using top-down and bottom-up flows.

Fusion Compiler Frontend

Learn to use Fusion Compiler to perform physical synthesis using the compile_fusion command, which unifies traditional synthesis with placement and optimization, along with additional physical design techniques such as concurrent clock and data optimization.

SystemVerilog for RTL Design

In this course, you will learn how to achieve high quality of results for your RTL design using SystemVerilog. It is assumed that you are versed in Verilog and want to improve your RTL coding efficiency with SystemVerilog.

TestMAX Advisor (SpyGlass DFT)

In this workshop, you will learn to use TestMAX Advisor (previously known as SpyGlass DFT) to perform RTL testability analysis that will allow you to fine-tune your RTL early in the design cycle. This will verify the design scan readiness and Test Robustness and work towards meeting fault and test coverage goals.