Global Unichip Corp. (GUC) is a leading provider of advanced ASIC and SoC manufacturing services, based in Taiwan. Specializing in high-performance computing (HPC), artificial intelligence (AI), mobile, automotive, and IoT designs, GUC has a proven track record of maximizing power and performance while ensuring rapid time-to-market for its customers. With the increasing complexity of chip designs, including thousands of macros in their SoCs, GUC faced significant challenges in maintaining productivity and quality in their floorplanning processes.

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GUC faced several critical challenges in their floorplanning process:
  • Increased Design Complexity: The growing number of macros, exceeding 2000 in some SoCs, made manual floorplanning time-consuming and error-prone.
  • Aggressive Quality-of-Results (QoR) Goals: Meeting high QoR targets with fewer floorplan iterations was becoming increasingly difficult.
  • Time Constraints: The manual trial-and-error approach to floorplanning was dominating project schedules, delaying time-to-market.


To address these challenges, GUC implemented Synopsys IC Compiler™ II and Synopsys Fusion Compiler™ P&R solutions, leveraging the FreeForm Macro Placement technology. This technology automates the floorplanning process, significantly reducing the time and effort required. Key features of the solution include:

  • Automation and Intelligence: The FreeForm Macro Placement technology automates the placement of macros and standard cells, optimizing wirelength, timing, and power.
  • Congestion-Aware Placement: The technology is designed to be congestion-aware, ensuring better quality-of-results (QoR).
  • Machine Learning Integration: The next-generation Machine Learning-Driven Macro Placement technology predicts congestion, wirelength, and total negative slack (TNS), reducing manual tuning efforts.


The implementation of Synopsys' FreeForm Macro Placement technology brought significant benefits to GUC:

  • Reduced Design Time: Dramatically reduced floorplan design time, enabling GUC to meet aggressive ASIC design schedules.
  • Improved PPA Metrics: Achieved 14% reduced switching power, 19% wirelength reduction, lower leakage power, and zero glitch violations, resulting in better signal integrity.
  • Enhanced Productivity: Allowed GUC to streamline design cycles for complex SoCs with thousands of macros, increasing P&R productivity.

By leveraging Synopsys' advanced floorplanning technologies, GUC was able to accelerate their design process, achieving optimal timing and congestion while reducing the number of floorplan iterations. This collaboration has enabled GUC to deliver best-in-class PPA metrics for demanding designs in areas such as next-generation AI hardware, HPC, automotive, mobile, and IoT.