1:1 with Vineet Rashingkar

Picture of Joe Jarzombek

RTL Architect in Aerospace and Defense

We sat down with Vineet Rashingkar, R&D Director in Synopsys’ Design Group, to learn how the Synopsys RTL Architect™ leverages state-of-the-art commercial technology to benefit Aerospace and Defense designs.

Q: Welcome Vineet. Can you tell us more about RTL Architect and its applications in Aerospace and Defense?

We have seen that our Aerospace and Defense customers design challenges have changed in recent years. Previously, the focus was on FPGA design with a fraction of designs going to ASICs and SoCs. Today, there is an additional element being added to that realm: customers are building not only ASICs, SoCs, and FPGAs, but also heterogenous systems-in-a-package (SiP). Of course, SiPs often have one or more ASIC or FPGA elements embedded within those domain or application-targeted efforts.

RTL Architect is targeted at customers building ASICs, SoCs, and SiPs. This product helps design teams achieve PPA goals even with the challenges of increased complexity in advanced process nodes. In addition, the emergence of AI, chip-package co-design, and early hardware-software debug require customers to do early and rapid architecture exploration. These challenges put pressure on RTL designers to dramatically improve RTL quality prior to implementation feedback and before the RTL-to-GDSII flow. However, the process today is not efficient since it lacks a platform for developers to accurately measure the impact of their RTL modifications.

Synopsys’ RTL Architect is the industry’s first physically aware RTL analysis, optimization, and signoff system, built from the ground up for superior RTL handoff. It enables RTL designers to quickly achieve superior RTL and reduces the SoC implementation cycle in half.

 

Q: Who are the target users for RTL Architect?

RTL Architect benefits SoC and IP RTL designers as well as front-end implementation teams. SoC and IP RTL designers can perform rapid architectural explorations to achieve the best design PPA. Architects and designers can also handoff implementable RTL with confidence. SoC integrators and RTL synthesis teams, on the other hand, can use RTL Architect as a checkpoint for RTL as it enters the digital implementation flow.

 

Q: How does RTL Architect offer a more cohesive solution than alternative offerings?

Existing point tool solutions for estimating RTL quality are severely limited due to poor accuracy to downstream implementation. These early design cycle inaccuracies cause downstream tools to compensate, causing several RTL iterations to meet PPA goals. The fragmented solutions today are not physically aware and are optimizing for single cost functions. RTL Architect is uniquely positioned to address these challenges as it directly leverages Synopsys’ world-class implementation and golden signoff solutions to deliver results that correlate-by-construction early in the design cycle.

 

Q: Can you elaborate on the innovative technologies in RTL Architect?

The core differentiating technology in RTL Architect is its fast, multi-dimensional predictive engine that enables RTL designers to predict power, performance, area, and the impact of congestion on their RTL changes. With this tool designers can now pinpoint inefficiencies in their HDL source code and improve its quality.

RTL Architect shares many of the technologies available in the Synopsys Fusion Design Platform. Specifically, the unified Fusion data model provides unprecedented capacity, scalability, and comprehensive hierarchical design capabilities to address the growing needs for advanced node designs. Another key technology is the integration with Synopsys’ PrimePower golden signoff power analysis engine to enable accurate RTL power estimation and optimization for energy-efficient designs.

Finally, the product provides RTL restructuring, constraints management, and cross-probing capabilities to provide early insights into key quality metrics.

 

Q: When in the development cycle should customers use RTL Architect?

Screen image of RTL Architect GUI

RTL Architect is designed to be used throughout the RTL development cycle. For example, at early stages, restructuring and floorplanning features will be used more frequently. Later, during the development phase, congestion, timing, and power feedback can be used to tune code quality.

Q: How does RTL Architect fit into the Synopsys Fusion Design Platform?

RTL Architect is part of the Synopsys Fusion Design Platform that eliminates traditional boundaries between RTL developers and RTL synthesis teams. With its unique technologies and the foundation of Synopsys’ world-class engines, RTL Architect can be the gateway for entry into RTL-to-GDSII flow.

 

Q: Thank you Vineet for joining us for this insightful discussion on Synopsys RTL Architect. Any closing remarks?

You are welcome! We are very excited about our ability to better serve our Aerospace and Defense customers with state-of-the-art tools and methodologies like RTL Architect, Fusion Compiler, and the Fusion Design Platform. Our commercial RTL architect customers are observing the benefit of quick, early, and accurate RTL analysis in their development cycle that results in faster time-to-deployment and improved productivity. We look forward to working with our Aerospace and Defense customer base to enable shift-left for RTL design closure with RTL Architect.