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A Must-Attend Event
This series has three tracks with multiple sessions per track showcasing the latest advancements in Digital Design technologies. The Series runs over three weeks, sessions are for a couple of hours each day. You can choose the tracks and sessions you would like to attend. These sessions will run on Zoom and will be recorded. All times listed are in CET (Central European Time)
Who Should Attend?
Front-end, back-end, synthesis, physical design engineers, project leaders, physical design and CAD team managers are the primary audience. Attendance at this event is free, but registration is required, once you have registered the Zoom meeting invitation will be sent separately.
Agenda-At-A-Glance
Track #1: Design Compiler NXT and IC Compiler II
Design Compiler NXT Session 1 | Monday, March 8 | 9:30 -11:00 a.m.
Highlights key PPA enabling technologies introduced in latest releases. Introduces the IC Compiler II link and NDM library support that is essential to supporting complex and advanced node designs.
Design Compiler NXT Session 2 | Tuesday, March 9 | 9:30 - 11:00 a.m.
Provides a deep dive into the workings of the IC Compiler II link and offers practical tips on congestion debug and dirty data handling.
IC Compiler II Session 1 | Monday, March 15 | 9:30 - 11:00 a.m.
Introduces the Reference Methodology (RM) and low power flows. Offers a practical guide to improving flow runtimes.
IC Compiler II Session 2 | Tuesday March 16 | 9:30 - 11:00 a.m.
Covers the latest technology improvements in IC Compiler II including early data handling, global route everywhere, post-route design and eco fusion technologies.
Track #2: Fusion Compiler
Fusion Compiler Session 1 | Wednesday, March 10 | 4:00 - 6:00 p.m.
Introduces the Reference Methodology (RM) and low power flows. Highlights new synthesis advancements including clock gate latency estimation and shift-left Design for Test (DFT).
Fusion Compiler Session 2 | Thursday, March 11 | 9:30 - 11:00 a.m.
Covers the latest technology improvements in Fusion Compiler including early data handling, global route everywhere, post-route design and eco fusion technologies. Offers a practical guide to improving flow runtimes.
RTL Architect & Machine Learning | Wednesday, March 17 | 4:00 - 5:30 p.m.
Introduces RTL Architect, a complete RTL analysis and optimization solution that enables early RTL exploration to achieve predictable RTL closure and improved power, performance, and area metrics in less development time. The second half of this session showcases machine learning technologies spanning the full flow.
Fusion Compiler Session 3 | Thursday March 18 | 9:30 - 11:00 a.m.
Offers a practical guide to analyze and address quality of results and runtime challenges. Focuses on synthesis technologies, useful commands and debug methodologies to improve timing, area, power, congestion and time to results.
Track #3: RTL to GDSII Flows & Debug
Advanced Nodes & RedHawk Analysis Fusion | Monday, March 22 | 9:30 - 11:00 a.m.
Showcases 6-nm and 5-nm advanced node support in place and route. The second half of this session covers the Red Hawk Fusion flow for power integrity.
Hierarchical Design | Tuesday, March 23 | 9:30 - 11:00 a.m.
Highlights enabling technologies for top-level design planning and implementation including freeform macro placement, floorplanning for advanced nodes, clock trunk planning and hierarchical modeling.
Multivoltage/Power Analysis | Wednesday, March 24 | 2:00 - 4:30 p.m.
Offers a practical guide to debug multi-voltage/UPF and power analysis/activity annotation issues across the full flow. Covering Design Compiler NXT and Fusion Compiler.
