Fusion Compiler Session 1 | Wednesday, March 10 | 4:00 - 6:00 p.m.
Introduces the Reference Methodology (RM) and low power flows. Highlights new synthesis advancements including clock gate latency estimation and shift-left Design for Test (DFT).
Fusion Compiler Session 2 | Thursday, March 11 | 9:30 - 11:00 a.m.
Covers the latest technology improvements in Fusion Compiler including early data handling, global route everywhere, post-route design and eco fusion technologies. Offers a practical guide to improving flow runtimes.
RTL Architect & Machine Learning | Wednesday, March 17 | 4:00 - 5:30 p.m.
Introduces RTL Architect, a complete RTL analysis and optimization solution that enables early RTL exploration to achieve predictable RTL closure and improved power, performance, and area metrics in less development time. The second half of this session showcases machine learning technologies spanning the full flow.
Fusion Compiler Session 3 | Thursday March 18 | 9:30 - 11:00 a.m.
Offers a practical guide to analyze and address quality of results and runtime challenges. Focuses on synthesis technologies, useful commands and debug methodologies to improve timing, area, power, congestion and time to results.