The Schedule Squeeze
We’ve all been there; that ghostly, ethereal sound we hear (or maybe just feel) as the deadline or milestone that we were aiming to achieve, sails ingloriously by. In design it happens time and time again: the RTL is late because architectural refinements were needed, the netlist is late because said architecture wasn’t feasible, the routed design struggles with convergence as we’re pushing the boundaries of what is possible with the library and PVT constraints…… and then poor “Brad,” that lovely guy with a new family but our long-time, go-to-bat, signoff guy, gets to spend his summer vacation working on signoff ECOs to close out that last mile for the design. Sound familiar?
The issue is that Brad has a cliff-edge to work against – the ever present, and maybe increasingly aggressive, first-to-market windows. Our valiant and unstoppable, signoff-closure force has to reckon with the immovable object of tape-out windows.
It doesn’t help that the signoff challenge grows ever more pernicious; timing-corner expansion associated with advanced-process effects, put noise into the mix to capture accurate waveform distortion (and it’s not so subtle) subtilties and with IR-drop making-or-breaking a design, the schedule squeeze is real and getting ever more difficult to contain.
Fortunately, we’re dealing with a false paradox. Immovable deadlines do exist, but the unstoppable force is bettered, bolstered or grossly-enhanced by improvable design methodologies.
The “Path to Signoff”
Signoff is the gate-keeper. It’s the explicit agreement that if we meet the entry-point for the needs of the process, that through all the foundry magic – held tightly in their closely-guarded trade secrets – we will see a glorious interplay and what we tape-out, will work. The product that we’re pouring person-years into – it’s all very egalitarian on the front-line of first-to-market products – will yield and our new product idea will have the opportunity to take flight.
The problem becomes clear that design closure is not Brad’s problem. Or at least it shouldn’t all be. Sure, when we start to sign off across hundreds of corners, unoptimized paths or incorrectly optimized paths will show up. However, they should be few and bounded in scope. The solution lays in thinking differently, with how we have always done things in the past – where you’ll always get, what you always got – and pivoting to something better.
Better by Design
With three clocks or timing-engines in play – synthesis timing, place-and-route timing and signoff timing – measuring and enforcing timeliness can become challenging. It’s not because all accuracies need to be equal – “Call me after lunch on Wednesday” is likely good enough for the early stages of synthesis, even if “Call me on Wednesday at 2:45 pm” is what signoff eventually enforces. The key lays in that they all need to model the timing view in a consistent way. If everything is being equally measured across a single timing context, we can start to remove the methodology-centric margins from the flow – those between synthesis and place and route, and between place and route and signoff – and this builds the framework for a zero-margin methodology.
Accuracy is of course important. “Golden accuracy” status is an important measure and is determined by the foundry as the signoff tools meeting the determined accuracy bar for the process. The “industry favorite” or “most trusted” accolades, however, are far more difficult to attain as it only comes when customers are willing to “bet the farm” time-and-time again on your products – when they feel comfortable and confident that you will continue to deliver best-in-class solutions and help them experience right-first-time silicon. Synopsys holds the “industry favorite” and “most trusted” status across the wide breadth of the signoff portfolio thanks to continuous innovation and strong investment in differentiated tools. Being able to bring this lauded signoff accuracy closer to the design process again allows for margin reduction – towards the zero-margin methodology – but moreover, it brings a more convergent closure experience as all optimization steps can, at the appropriate time, see full accuracy and so not over-design or ping-pong between optimization positions.
Doing it Differently – One Golden-Signoff-Capable Timing Engine to Rule them All
With Fusion Compiler, we were able to take all these ideas of “the right way to do it” and approach the problem of digital implementation differently. Once you have a unified data-model as the cornerstone of the products’ implementation, deploying a single analysis fabric is not only easier, more robust and more compact but also makes glaringly obvious sense. Taking the industry’s most trusted delay model from PrimeTime™, including all the library setup, SI and timing-window modeling, makes for a hugely optimized-and-efficient design flow as we can maintain a single timing setup from RTL all the way to tape-out.
We now are able to help “Brad” out – or maybe YOU are that sign-off person. Our design flow becomes more convergent and optimized as we have wrung out the flow-centric margins between the tools and also enabled signoff design closure to be part of the block closure flow. Gone are the timing bumps between synthesis and place-and-route, and place-and-route can now complete with only those outlier paths, those found in the 200th corner. Ultimately, “Brad” gets his vacation and our design has better PPA as our zero-margin methodology ensured that we didn’t overdesign.
Simpler is better and Fusion Compiler enables Simply Better PPA.