Synopsys Synplify® Premier software offers FPGA designers an automated means to build into their design functional safety, high uptimes, and highly reliable design operation. These designs become resistant to radiation-induced errors and other single bit flips that might otherwise result in incorrect operation or, even, system lock-up. As FPGA device geometries shrink, this solution is becoming a “must have” for systems deployed in industrial, medical, automotive, communications, military and aerospace applications.
Industry standards including DO-254, IEC 61508 and ISO 26262 define functional safety and error mitigation strategies for the creation and validation of high reliability systems. The Synplify Premier tool automates industry methods for mitigating soft errors such as single-event upsets (SEUs) that are increasingly present in the latest FPGA process geometries. Synplify Premier provides two essential elements to automate SEU immunity and create safe designs that operate with high reliability in radiation-rich environments.
- Direct support for SEU error detection and recovery schemes across all FPGA device families from Altera, Lattice, Microsemi and Xilinx
- Automated support for the creation of SEU error monitors, enabling software-based error mitigation schemes for controlling, monitoring, recovery and diagnostics of system errors that occurred due to SEUs