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DesignWare ARC 770D Processor Core
The DesignWare® ARC® 770D 32-bit processor core incorporates a Linux acceleration package that delivers up to 30% higher performance running Linux, Android or other high-end operating systems. The extremely power and area efficient ARC 770D processor core is ideal for embedded multi-core and portable applications. The highly configurable processor core allows SoC designers to include only the processor features required for their specific application, resulting in smaller die size and lower power compared to a fixed architecture core.
The ARC 770D processor core requires less than half the die area and half the power compared to other cores that are similar in configuration and speed. In addition, optional custom extensions may be incorporated to achieve application performance levels unattainable with fixed architecture cores. The instruction and data caches of the ARC 770D processor core accelerate processing and keep implementation size and power consumption to a minimum. The enhanced Memory Management Unit (MMU) is designed for complex SoCs running Android, Linux or other high-end operating systems.
The ARC 770D processor core is supported by a full suite of software and hardware development tools. The suite includes the MetaWare Development Kit, which generates highly efficient code that is ideal for deeply embedded applications, the DesignWare ARC simulators including xCAM and nSIM and the DesignWare ARChitect configuration tool.
Figure 1: DesignWare ARC 770D Block Diagram
Register for the ARC 700 Processor Online Training
- Highly configurable 32-bit processor core
- Linux acceleration package including shared library address space identifier (ASID) support in MMU and load lock/store conditional instructions
- MMU-based memory solution supports Linux and other high-end operating systems
- Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms
- Optional DesignWare ARC XY Advanced DSP solution delivers the performance of dedicated DSP cores, allowing external logic and DSP blocks to be eliminated
- DesignWare ARCompact™ 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets
- JTAG debug port and optional embedded hardware breakpoints facilitate software debug
- Delivered as synthesizable RTL source code (Verilog®), fully compatible with industry standard design methodologies and tool flows