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The Synopsys ARC® 750D 32-bit configurable processor core is ideal for complex system-on-chips (SoCs) running Linux, Android or other high-end operating systems. It is a complete application processor for home entertainment systems, portable devices such as smartphones, automotive telematics systems and many other information-based products. In addition, optional custom extensions may be incorporated to achieve application performance levels unattainable with fixed architecture cores.
The Synopsys ARC 750D processor core is supported by a full suite of software and hardware development tools. The suite includes the MetaWare Development Kit, which generates highly efficient code that is ideal for embedded applications and ARC simulators including xCAM and nSIM, and the ARChitect configuration tool.
Highlights & Key Features
- A highly configurable architecture allows SoC designers to include only the core features that are required for their specific application, resulting in smaller die size and lower power than can be achieved with a fixed core.
- User-defined instruction and register extensions deliver 5 - 100 times performance improvement of critical routines.
- Instruction and data cache support and closely coupled (single-cycle) memories provide fast, predictable computation.
- Memory Management Unit (MMU) to support high-end operating systems such as Linux and Android.
- Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms.
- Optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores.
- Synopsys ARCompact™ 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets.
- Inter-core communication ISA support, multi-core debug environment and flexible interfaces enable multi-core designs.
- JTAG debug port and optional embedded hardware breakpoints facilitate software debug.
- Delivered as synthesizable RTL source code (Verilog®), the Synopsys ARC 750D core is fully compatible with industry standard design methodologies and tool flows.
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