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The Synopsys ARC® 610D configurable 32-bit processor core is designed for hard, real-time processing, where high speed and deterministic response are required. The processor core is widely used and ideal for a broad range of embedded control computing functions within system-on-chip (SoC) applications that include conventional computation, digital signal processing (DSP) algorithms and advanced power management capabilities.
DSP options enable the processor core to efficiently perform signal processing tasks by consolidating the development environment and eliminating the need for separate logic or DSP blocks from the SoC. The high-performance and high-speed ARC 610D processor core features a zero-overhead loop which reduces code size in highly integrated SoC designs. The core offers dedicated registers that enable parallel execution of its 16- and 32-bit multiplier (MUL) and multiply accumulate (MAC) instructions and other arithmetic logic unit (ALU) operations.
With the capability of incorporating custom floating point unit (FPU) and a memory protection unit (MPU), the processor core can achieve application performance levels unattainable with fixed architecture cores. Full DSP performance is achieved through the use of the configurable banks of the XY memory which includes support from the ARC DSPlib with extensions such as Dual FFT, Viterbi, CRC and 24 x 24 MAC.
The Synopsys ARC processors are designed with a 16-/32-bit instruction set architecture that provides high code density with no overhead for switching between 16- and 32-bit instructions. With flexible addressing modes, the ARC 610D provides up to 128 dual or single operand instruction codes available for user-defined extensions and up to 64 directly addressable core registers and 32 conditional execution codes.
The ARC 610D processor core is supported by a full suite of software and hardware development tools. The suite includes the acclaimed MetaWare Development Kit that generates highly efficient code ideal for deeply embedded applications, the ARC simulators including xCAM and nSIM, and the ARChitect configuration tool.
Highlights & Key Features
- 5-stage instruction pipeline
- Static branch prediction
- 32-bit data, instruction and address buses
- Score-boarded data memory pipeline to reduce stalls
- Single-cycle instruction CCM (Closely Coupled Memory), 1 KB - 512 KB
- Single-cycle data CCM, 2 KB - 256 KB
- Up to 32, two level interrupts
- Up to 128 dual or single operand instruction codes available for user-defined instructions
- 16 or 32 entry register file in base core, extendible to 60 registers
- 32-bit auxiliary register space for single-cycle, unarbitrated data storage and retrieval
- 16- and 32-bit MUL and MAC instructions
- Zero overhead loop support
- Full DSP performance using configurable banks of XY memory
- Optional Floating Point Unit
- Sleep mode via software instruction
- Debug host can access all registers and CPU memory
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