The inline ECC scheme is typically implemented in applications using LPDDR memories. As the LPDDR DRAMs have a fixed-channel width (16-bits for a LPDDR5/4/4X channel), side-band ECC becomes an expensive solution with these memories. For instance, for a 16-bit data-width, an additional 16-bit LPDDR channel needs to be allocated for side-band ECC for the 7 or 8-bit ECC code-word. Moreover, the 7- or 8-bit ECC code-word fills the 16-bit additional channel only partially, resulting in storage inefficiency and also adding extra load to the address command channel, possibly limiting performance. Hence, Inline ECC becomes a better solution for LPDDR memories.
Instead of requiring an additional channel for ECC storage, the controller in inline ECC stores the ECC code in the same DRAM channel where the actual data is stored. Hence, the overall data-width of the memory channel remains the same as the actual data-width.
In Inline ECC, the 16-bit channel memory is partitioned such that a dedicated fraction of the memory is allocated to ECC code storage. When the ECC code is not sent along with the WR and RD data, the controller generates separate overhead WR and RD commands for ECC codes. Hence, every WR and RD command for the actual data is accompanied with an overhead WR and RD command respectively for the ECC data. High-performance controllers reduce the penalty of such overhead ECC commands by packing the ECC data of several consecutive addresses in one overhead ECC WR command. Similarly, the controller reads the ECC data of several consecutive addresses from memory in one overhead ECC RD command and can apply the read-out ECC data to the actual data from the consecutive addresses. Hence, the more sequential the traffic pattern is, the latency penalty is less due to such ECC overhead commands. Figure 3 describes the WR and RD operation flows with inline ECC.