Aparna Tarde

Aparna Tarde is a Sr. Staff Technical Product Manager responsible for the die-to-die interface IP product line at Synopsys. She previously worked as a design engineer at Intel designing cloud-based accelerator systems using PCIe, Ethernet, and DDR. She has also held different positions from design verification to applications engineering and has extensive knowledge in system design using FPGAs in data centers. She holds a master's degree in electrical engineering from San Jose State University.