Any Tool. Any Scale. Any Time.
Madhumita Sanyal, Technical Marketing Manager, Synopsys
The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25Tb/s (terabytes) to 51Tb/s and soon to 100Tb/s. The industry has chosen Ethernet to drive the switch market, using 112G SerDes or PHY technology today and 224G SerDes in the future. As Andreas Bechtolsheim, co-founder and Chairman of Arista Network, highlights in Figure 1, the deployment of 112G SerDes will peak by 2025. This article describes how designers can overcome design challenges, such as power, area, packaging, signal integrity, power integrity and 800G Ethernet implementation for HPC systems using 112G Ethernet PHY IP.
Area and Power
Reducing power and area while transitioning to more advanced process technologies from 7nm to 5nm to 3nm becomes a key focus as the use of lower power modulation, such as PAM-4, and high speed SerDes technology, such as 112 Ethernet PHY, increases. In addition, there are die size limitations due to yield issues. Denser integration of components in the Ethernet switch SoC is required to maintain the same size since server boxes and compute boxes must fit in the same chassis in the rack units, as seen in Figure 2.
However, such dense integration of SoC components is increasing power and requiring expensive cooling systems. All of these make area, power and latency key metrics or challenges for high-density switches. They also impact performance as SoCs for switches incorporate hundreds of lanes, making system performance more important than a single SerDes performance.
Transition to Co-Packaged Optics
Data center optics is also evolving to support the higher bandwidth networking demands. Both optics and ASICs have to address area, power and latency challenges within the switch-optic interconnects and minimize the switch-optic electrical I/O power consumption. Figure 3 shows the evolution of power in pluggable optics, which is the technology of choice today.
Figure 4: Gaps between the top X4 macro and bottom flipped X4 macro appear if PCS and MAC are placed in between them for timing closure flexibility
The above implementation might not be feasible for high-speed signal escapes on the north and south die edges. Various floorplan tryouts that need months of trial and error, such as placing the individual blocks in the required channel and minimizing the core die area, contribute to schedule delays. Top-down approach with a specified bounding box is becoming essential due to 100s of lanes in a design and limited die area and beachfront. Tile-like implementation can ensure reusability and seamless integration in all die edges.
112G SerDes or PHY is driving the next generation of compute, storage and networking innovations in cloud data centers for high-performance computing and AI/ML. Ethernet switch SoC designers implementing 112G SerDes or PHY technology must consider a slew of critical metrics or challenges, such as power, area, latency, die stacking, signal integrity, power integrity, and implementation, all of which are tasks that add to designers’ already short design schedules.
With the silicon-proven, PAM-4 112G Ethernet PHY in advanced FinFET nodes, along with PCS, MAC and cutting-edge AI/ML-driven EDA tools, Synopsys is enabling SoC designers to achieve the best power, performance, area and latency, while addressing system reliability, power integrity and signal integrity.
Synopsys has performed all the required work, such as package escape studies, PHY, SRAMs, PCS and MAC placement optimization including partitioning and floorplanning, pin placement, place and route, timing closure and signoff electromigration/IR drop analysis, helping users successfully tape-out large-scale SoCs with hundreds of lanes of 112G SerDes instantiations. Synopsys can deliver such a comprehensive solution by leveraging our logic libraries, memory compilers, EDA tools, system solutions such as 3DIC, integrated 3rd-party tools like Apache/Redhawk, and close collaboration with PHY, MAC, PCS designers, as well as implementation and system experts. Synopsys provides integration-friendly deliverables for 112G Ethernet PHY, PCS and MAC with expert-level support which can make customers’ life easier by reducing design cycles and helping to bring products to market faster.