DesignWare ARC Processor Cores

DesignWare ARC SEM Security Processors with SecureShield Technology

Protect against side-channel attacks, IP theft and data breaches in low-power embedded applications

Accelerating Development of Performance-Efficient SoCs

Synopsys' DesignWare® ARC® Processors are a family of 32-bit CPUs that SoC designers can optimize for a wide range of uses, from deeply embedded to high-performance host applications in a variety of market segments. Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements. The DesignWare ARC processors are also extendable, allowing designers to add their own custom instructions that dramatically increase performance. Synopsys' ARC processors have been used by over 225 customers worldwide who collectively ship more than 1.9 billion ARC-based chips annually.

All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent performance and code density for embedded and host SoC applications. The RISC microprocessors are synthesizable and can be implemented in any foundry or process, and are supported by a complete ecosystem of commercial and open-source tools for software development.

DesignWare ARC processors are supported by a broad ecosystem of commercial and open source tools, operating systems and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC Open Software Platform.

Jump to: MarketsPPA EfficiencyConfigurabilityExtensibilityAPEX Interface

Markets

Synopsys' broad portfolio of DesignWare® ARC® Processors includes a variety of 32-bit CPUs from power-efficient to high-performance cores that SoC designers can optimize for a wide range of uses, including embedded and deeply embedded applications. Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet the specific performance, power and area requirements of their mobile, IoT, digital home, automotive, industrial and storage applications. 

PPA Efficiency

The ARC Advantage: Maximum Performance With Minimum Area and Power

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.

ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.

Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

Configurability

The ARC Advantage: Implement Only the Hardware You Need to Optimize PPA

ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed. The ARChitect wizard enables drag-and-drop configuration of the core, including options for

  • Instruction, program counter and loop counter widths
  • Register file size
  • Timers, reset and interrupts
  • Byte ordering
  • Memory type, size, partitioning, base address
  • Power management, clock gating
  • Ports and bus protocol
  • Multipliers, dividers and other hardware features
  • Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT)
  • Adding/removing instructions

Extensibility

The ARC Advantage: Add User-Defined Instructions to Accelerate Code Execution and Lower Power Consumption

ARC Processor EXtension (APEX) technology enables ARC users to easily add their own custom hardware to the processor, dramatically boosting performance and/or reducing power consumption for their targeted application(s). ARC processors can be extended with:

  • User-defined instructions
  • User-supplied hardware (e.g., Verilog RTL)
  • Core registers
  • Auxiliary registers
  • Condition & status codes
  • Memory mapped blocks and closely coupled peripherals

ARC processor extensions enable users to dramatically improve performance, power and area. User-defined instructions, for example, can accelerate software execution, enabling the same code to run in much fewer cycles which reduces energy consumption by lowering clock frequency requirements (or enables the execution of more operations with the same energy.) Code size is also reduced, lowering memory requirements which leads to additional cost and power savings. 

APEX Interface

The APEX interface also enables ARC users to tightly couple memory and peripherals to the processor, eliminating the need for additional bus infrastructure. The resulting "bus-less" design further reduces area and latency, increasing system-level performance while reducing costs.