Scale When You Need for Better All-Around Results

Chip design processes require substantial compute resources, but not always in a predictable way. With Synopsys cloud-based design solutions, you can scale as needed in a secure environment for enhanced productivity and reduced turnaround time and costs. Production proven on major public cloud platforms, our solutions are endorsed by major semiconductor foundries to work with their libraries and process design kits.


Cloud-Optimized Solutions

Fusion Design Platform | Synopsys

Better PPA with RTL-to-Signoff Flow in the Cloud 

The success of advanced designs depends, in part, on foreseeable quality-of-results. Achieve faster time-to-results and predictable PPA with Synopsys Fusion Design Platform in the cloud. Experience 5x faster throughput by scaling optimization workloads in the cloud with increased threading and distributed computing. Leverage cloud compute resources to expand deployment of machine learning technologies throughout RTL-to-signoff to reduce design iterations and realize predictable implementation success.   ​

PrimeLib | Synopsys

Improve Delivery Time By 10X

High-quality libraries are essential building blocks for SoC designs, but the timely availability of them for advanced process nodes is often a critical bottleneck, potentially delaying project schedules. Library characterization typically takes months and, with each advanced node, the challenges grow to include a 3x increase of PVT corners, variation modeling, and reliability and aging effects. Synopsys PrimeLib includes key technologies to reduce IO and network traffic and minimize license server overhead, as well as checkpointing and recovery mechanisms. PrimeLib provides superior scalability to existing solutions beyond 100,000 parallel jobs on the cloud by delivering 10x faster turnaround time.

Signoff + -
Scalable Golden Signoff | Synopsys

Achieve 100x Faster Cloud Speed-Up and Golden Signoff

As we move to deeper submicron nodes, designers face significant performance and capacity challenges during the signoff design phase of their complex, ultra-large-scale SoCs. Synopsys PrimeTime® timing and Synopsys StarRC™ extraction signoff solutions are cloud-ready and have been built to run on massively parallel server farms, delivering fast, memory-efficient scalar, multicore, and distributed multi-scenario analysis and ECO fixing for silicon-accurate results.​ Synopsys signoff solutions also enable a hybrid cloud use model, dynamic cloud elasticity, scale-out of distributed compute/storage, and significant cloud scalability, delivering 100x faster turnaround time.

Custom Design Platform | Synopsys

Scalable and Efficient Custom Design on the Cloud

Today’s hyper-convergent SoCs are larger, faster, and more complex impacting time-to-results, quality-of-results, and cost-to-results across the entire custom design flow. The Synopsys Custom Design Platform is cloud ready with modern, scalable and highly efficient tools that accelerate custom design creation and signoff across leading public cloud service providers. The platform features Custom Compiler™, a fast, easy-to-use design, and layout solution, PrimeSim™ Continuum, which delivers industry-leading circuit simulation performance, and best-in-class technologies for parasitic extraction, reliability analysis, and physical verification. PrimeSim Continuum provides scalable performance for large distributed simulation workloads and heterogenous compute acceleration that leverages high performance CPU and GPU resources on the cloud to reduce circuit simulation time.

IC Validator | Synopsys

Verify Full-Chip Designs in Hours, Optimize Compute Usage

At advanced nodes, the turnaround time for physical verification closure has become quite challenging. Synopsys IC Validator provides a comprehensive and highly scalable physical verification solution that includes DRC, LVS, PERC, dummy metal fill, and DFM capabilities. A DRC or LVS job for a leading-edge design with billions of transistors can run for multiple days. IC Validator is architected for massive scalability to thousands of cores on the cloud, enabling completion of signoff jobs within hours. Its unique elastic CPU management technology means you can add and remove resources on-the-fly based on job needs, saving up to 40% in cloud compute resources.

DSO.ai: Design with AI | Synopsys

AI-Driven Design Applications

​With increasingly aggressive PPA and time-to-market demands on chips, designers need to enhance productivity while creating innovative new silicon solutions. Synopsys DSO.ai™ (Design Space Optimization AI), the industry’s first autonomous artificial intelligence application for chip design, is one way to do this. With its powerful reinforcement learning engine, the award-winning DSO.ai massively scales the exploration of options in chip design workflows, automating less consequential decisions. While DSO.ai increases the efficiency of today’s on-prem compute environments, it's also optimized to execute its computations in the cloud, offering the ability to scale compute on-demand for even better PPA. ​​

How EDA in the Cloud Fuels Semiconductor Innovation

Innovation Blog Series

Explore Our Webinars

On-demand, in-depth technical information you need to accelerate chip design and verification in the cloud.

Essential Resources

Start Your Cloud Innovation Journey Today