Zephyr RTOS is the Core of Synopsys Silicon Lifecycle Management Solution

Marta Plantykow

May 30, 2024 / 5 min read

Within the world of digital technology, the journey of a product, from conception to its eventual obsolescence is convoluted and multifaceted. Increasing chip and system complexities coupled with escalating demands for performance and reliability drive the need for ongoing maintenance and optimization of semiconductor devices throughout their entire lifecycle. Synopsys' Silicon Lifecycle Management (SLM) solution rises as the potential hero in this narrative by providing a comprehensive roadmap not only for reliability and performance, but also for efficiency and sustainability.

zephyr rtos silicon lifecycle management

Continuous Silicon Health Monitoring

This innovative technology continuously, intelligently, and efficiently collects, tags, and stores all types of silicon monitor data allowing for analysis and optimization during the design, manufacturing, testing, and deployment of semiconductors in end-user systems.

semiconductor monitoring sensors

Figure 1: SLM sensors and monitors in an example implementation

Process, voltage, and temperature (PVT) sensors (semiconductor IP circuits), are usually integrated into System-on-Chip (SoC) devices. They are designed to constantly monitor the dynamic operating environment, including voltage and temperature, as well as the specific silicon performance. These sensors not only allow for the detection of anomalies but also help optimize the performance and power consumption of the device. 

The Path Margin Monitor (PMM) provides a crucial measurement of the timing margin of a selected path, which can be used to analyze and optimize any phase of the silicon lifecycle. This data is essential for monitoring the health of the silicon structure and assessing the aging process.

Dedicated controllers manage all sensors, handle the configuration and data collection, and provide data to a dedicated embedded processor (e.g. Synopsys ARC®) upon request.

Advanced Chip Data Processing Algorithms

SLM health monitoring algorithms, operating on the embedded processor, are engineered to examine the circuit behavior anomalies and detect stress, delay margin degradation, and defects. Such anomalies, which at times are severe enough to warrant further investigation, are central to the efficiency of the Synopsys SLM solution. Thanks to the degradation information, utilizing appropriate algorithms, SLM can estimate the remaining useful life of the SoC. Additionally, by leveraging data from sensors, the Synopsys SLM solution is not only capable of assessing the SoC condition but also can be utilized to optimize performance using techniques such as Vmin optimization or adaptive voltage scaling. Leveraging inference engines, significance can be assigned to identified issues triggering notifications to the application layer of the host processor for in-depth evaluation.

silicon lifecycle management use cases

Figure 2: SLM Use Cases

Synopsys ARC Core & Zephyr RTOS Support

Synopsys’ SLM solution can easily be tailored to meet the unique requirements of individual designs or use cases, defined at the design stage. To assist customers in building their own solutions, Synopsys offers a reference design that includes example code with configuration information and documentation. In this reference scenario, data is processed by SLM monitoring firmware running on a dedicated Synopsys ARC EM processor orchestrated by the Zephyr real-time operating system (RTOS).

The usage of an ultra-compact ARC EM core enables the SLM solution to achieve maximum performance with minimum power and area consumption. A 32-bit ARCv2 instruction set architecture (ISA) is optimized for a broad range of embedded applications, including safety support up to ASIL-D. Synopsys enables programmability for market-ready solution verticals on ARC cores by offering a choice and flexibility in operating systems.

A live demonstration of the SLM virtual platform showcased at Embedded World 2024 in Nuremberg in the Zephyr Project booth demonstrated Zephyr RTOS utilization in deeply embedded controllers, which is yet another application of Zephyr RTOS. The demo caught multiple visitors' attention as it conceptually differs from more obvious use cases with Zephyr RTOS running on small wearable devices, discrete sensors, etc.

zephyr rtos embedded world conference 2024

Figure 3: Silicon Lifecycle Management solution demo using SLM Virtual Platform, Embedded World Conference 2024

Zephyr RTOS was chosen for the SLM firmware reference implementation as it fully supports Synopsys ARC processors, ensuring a smooth development process. Additionally, high-quality, exhaustive documentation is available, along with meaningful examples. The Zephyr Project is being actively developed by the vibrant open-source community and is backed by the Linux Foundation. The developed implementation scales well from very low-end to higher-end embedded CPUs. Lastly, it's worth noting that Zephyr is becoming increasingly popular in the industry.

And just a small personal note: Linux kernel experience makes Zephyr implementations feel just like home.

Semiconductor Telemetry to the Cloud

The encrypted data traverses the path from the ARC core to the host processor; the host processor runs a Linux distribution in the reference design using a dedicated hardware mailbox implementation to ensure secure data transition and provide integrity of information exchange in the system. This communication uses the concept of a Mailbox, supported both in Linux and Zephyr, and is achieved using dedicated mailbox drivers and device tree entry on both operating systems.

cloud communication

Figure 4: ARC to Cloud communication

From the host processor, which in the reference design is connected to the outside world through ethernet, data may be forwarded to the cloud GUI offering further functionalities, such as automotive fleet monitoring or data center monitoring and more.

cloud gui

Figure 5: SLM Cloud GUI

Shift Left

The journey of designing and manufacturing new hardware is associated with risks and costs correlated to silicon re-spins. Virtual prototypes serve as invaluable tools to mitigate these challenges, allowing software development to start before hardware is physically available. Their remarkable debugging capabilities, facilitated by extensive control and visibility play a pivotal role in ensuring timely software development. The SLM reference design which consists of a dedicated ARC core working in concert with sensors and their controllers along with the host core connecting the environment with the external world, is developed using a tailored SLM virtual platform implemented using the Synopsys Virtualizer™ Development Kit (VDK) [8] environment. The SLM virtual platform supports two types of sensor and controller simulators: RTL-based, striving for loyal hardware features mapping, and alternatively, behavioral simulators prioritizing VP speed over accuracy. This strategic approach shifts solution development and full-stack verification earlier in the product lifecycle, empowering early demos and accelerating the innovation cycle.

At its core, Synopsys’ SLM solution embodies robust quality control measures, conducts thorough testing, facilitates timely maintenance and upgrades, and enhances reliability, performance, and dependability as a result. Efficiency is optimized through precise planning and resource allocation across every stage of the silicon lifecycle, from design and manufacturing to deployment and disposal. An SLM solution ensures that resources are utilized wisely, ultimately driving cost-effectiveness and productivity. Moreover, an SLM solution allows companies to incorporate sustainable practices such as recycling, refurbishment, and responsible disposal, to mitigate the environmental impact of silicon production and consumption.

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