Radiation is a major concern for semiconductors in space. Heavy ions trapped in the Earth’s magnetic field produce space radiation that impacts electronic components, typically in the form of a single event effect, or SEE, which stems from a single high-energy particle striking the device. An SEE can degrade system performance and even lead to its complete destruction. Total ionizing dose (TID) is another consequence of space radiation; it measures the effects of prolonged exposure to ionizing radiation.
Radiation-hardened (rad-hard) designs can blunt the impact of radiation-induced degradation, interruptions, and discontinuities in device performance. Space-based chips should also be designed to withstand a wide temperature range (-55◦ to 125◦C), frequent temperature cycles, electromigration, and interconnect aging.
To account for radiation-related effects, devices for space applications undergo radiation beam tests at an energy accelerator facility. The chip needs to be fabricated prior to testing, which means that the process of the design must be locked down. Such tests are expensive and require reserving a limited-availability time slot at the facility. Should a device fail the tests, it will have to be respun and resubmitted for testing. The next available time slot at the testing facility could be months away, further delaying production of the device and adding to its development costs.
Radiation modeling via TCAD can help engineers develop their designs to be more immune to the effects of radiation and, thus, be better prepared to undergo radiation beam tests, avoid respins, and reduce expensive beam time. TCAD provides a 3D physical representation of a transistor or several transistors. Device engineers and chip designers can then simulate electrical performance characteristics for insights. It’s possible to simulate what might happen if a particle strikes a transistor, or if the transistor gets hit by simultaneous particle strikes. When energy from a particle is transferred to the semiconductor, it generates additional charge particles (electrons and holes) that will alter the current at the transistor terminals; this is an example of an SEE. In critical circuit components, such as an SRAM bit cell, the changes in the terminal currents may lead to a change in the logic state of the component, leading to a soft (non-destructive) error. Similarly, the cumulative effects of radiation, which change the properties of transistors over time, can also be examined through modeling. Armed with these insights, device engineers and chip designers can determine how to best choose or optimize the process in which the transistor is fabricated as well as parameters such as the layout design in order to mitigate radiation effects.