Modern government, aerospace, and defense systems that perform automation and cognitive processing require a high computation density and, often, processing in a small form factor. For example, when it comes to high-performance computing (HPC) designs, monolithic SoCs are no longer capable of providing the scalability and yield that designers are looking for. Since almost all aspects of system performance are limited by power and electrical input/output (I/O), size and weight reduction are crucial objectives for designers.
By vertically or horizontally integrating different types of chips, 3DHI makes it possible to shrink big systems into small packages, leading to better computation as well as size, weight, and power (SWaP) of components — solving an important concern for space-constrained platforms (especially in harsh environments like the ocean, desert, and outer space). Smaller chips tend to yield better results and can be reused in different applications, creating new design possibilities. Moreover, owing to the proximity of these chips, 3D packages enable high-bandwidth, ultra-short-latency, and incredibly power-efficient bit transfers — a significant advantage over traditional 2D designs.
Increasing integration density has been a great benefit for realizing more capable and portable systems, but it has also raised serious multi-physics challenges. As demonstrated by Moore’s law, the geometric size of components on a chip cannot be reduced indefinitely, and sooner or later, the number of transistors that can be integrated on a chip will reach its limit. While we have yet to reach that stage, each technological miniaturization can take longer and be very costly.
The design and manufacturing complexity of 3DHI for challenging environments also translates to advancements in packaging technologies, interconnect solutions, and thermal management. This makes it more arduous for teams to ensure the reliable and efficient operation of integrated components for various external environments, including considerations for aircraft design assurance (DO-254/DO-178) and testing for the rigors of defense and aerospace with MIL-STD-883.
Unlike legacy EDA solutions that start from the PCB stage, Synopsys tools are unique because they can help co-design the die/package together, along with system signoff analysis. Finally, with the additional complexities around digital and analog processing, compound semiconductors, and supporting storage, memory, and photonics advancements, we see material and process engineering solutions playing a vital role in navigating integration intricacies with compound semiconductors as well as supporting existing defense designs and government research with a full tool flow for multi-die system designs.