How PCIe 7.0 is Boosting Bandwidth for AI Chips

Gary Ruggles, Priyank Shukla

Jun 10, 2024 / 3 min read

While headlines about the rapidly evolving nature of artificial intelligence (AI) continue to abound, the need for advanced and efficient hardware infrastructure is becoming more critical than ever before. Large language models (LLMs) continue to grow in complexity and double the number of parameters required every four to six months. In fact, GPT-4 has more than one trillion parameters! While this statistic is simple, the sheer amount of data this translates to is mind-boggling (2 trillion bytes or 200,000 high-resolution photos/500,000 documents). Moving these vast data sets requires robust, high-bandwidth interconnects to transfer all this information as fast and reliably as possible. 

Complex LLM algorithms and powerful accelerators/processors mean nothing if the data gets stuck in traffic bottlenecks. Current hyperscale data center infrastructures can’t keep up with the speed and low latency needed to process and store these models at scale. To change the game, hyperscalers and the entire supporting ecosystem need to consider transforming down to the silicon level to enable the scaling of systems that can handle petabyte-level data in real time while improving power efficiency. 

That’s where PCIe 7.0 comes into the picture, the latest iteration of the PCI Express standard. PCIe 7.0 offers up to 512 GB/s of bandwidth and ultra-low latency, and is poised to handle the massive parallel computing needs of AI workloads to help mitigate data bottlenecks. Today, Synopsys is launching the world's first complete PCIe 7.0 IP solution to enable secure data transfers and boost bandwidth for the next generation of AI and HPC chips.

pcie 7.0 ip ai hpc

Figure 1. The number of parameters in AI models doubles every 4 to 6 months, 4x faster than Moore’s Law, requiring more capacity, greater resources, and faster interconnects.

The Evolution of AI Infrastructure

Server rack units designed to support typical cloud applications have a straightforward setup: processors and Network Interface Cards (NICs) or Data Processing Units (DPUs) are connected via a PCIe link. 

ai hpc data centers pcie 7.0

Figure 2. The exponential increase in coherent compute demand requires next-generation CPU to accelerator links. 

However, as the complexity of AI models has ballooned, the infrastructure requirements to train these models have dramatically evolved. Modern AI workloads require a different architecture involving multiple accelerators working in tandem with a central processor. In fact, some of the most advanced architectures require connections of up to 1,024 accelerators within a computing unit. 

These accelerators need to be connected through an interconnect that supports a load-store architecture, which helps ensure that the processor can efficiently manage and process each packet of data. PCIe 7.0 offers the bandwidth and load-store capabilities necessary to connect multiple accelerators, enabling them to process large, complex machine learning models effectively. Additionally, PCIe 7.0 offers the required Ethernet bandwidth for processors to be connected with a network interface card compatible with 1.6 Tbps Ethernet links. 

To top it off, PCIe 7.0 can also support enhanced data security with the Integrity and Data Encryption (IDE) protocol to provide confidentiality, integrity, and replay protection for transaction layer packets (TLPs) and flow control units (FLITs). 

Synopsys PCIe 7.0 IP Solution Enables Scaling for AI Workloads and Reduces Integration Risk

As the leading provider of interface IP, Synopsys continues to enable the whole PCIe ecosystem, from processors and accelerators to flash controller, solid-state drive, retimers, Smart NICs, and switches. Synopsys brings over two decades of experience in PCIe IP and more than 3,000 design wins with leading companies.

pcie 7.0 ip

Highlights of the Synopsys PCIe 7.0 IP solution include: 

  • Improvement of interconnect power efficiency by up to 50% compared to prior PCIe generations
  • Low latency, high-bandwidth links with a full endpoint to root-complex solution that supports all required features for backward compatibility
  • Excellent signal integrity with speeds up to 128 Gb/s per lane enabling 512 GB/s PCIe systems
  • IDE security including data confidentiality, integrity, and replay protection against hardware-level attacks
  • Built-in protocol checks and multiple configurations of controller and PHY to accelerate verification and validation closure using Synopsys Verification IP
  • SoC Verification Kits to accelerate IP Integration sanity and reduce integration risks moving from IP to SoCs

Future-Proofing AI Infrastructure

For leading companies looking to stay at the forefront of innovation, investing in a trusted provider of PCIe 7.0 IP is not just an option; it's a necessity. This new technology promises to deliver the performance, scalability, and security needed to support the next wave of AI advancements, enabling designs that meet the ever-increasing demands and complexity of AI workloads. 

For more information on the Synopsys PCIe 7.0 IP solution, read the full press release here. And to learn even more, check out Synopsys’ two world-first demonstrations at the PCI-SIG Developers Conference on June 12 and 13, 2024: Synopsys PCI Express 7.0 PHY IP electrical-optical-electrical (E-O-E) will run at 128 Gb/s with OpenLight’s Photonic IC and Synopsys PCIe 7.0 Controller IP will show a successful root complex to endpoint connection with FLIT transfer. 

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