Since cars are expected to operate for more than 15 years, having reliable automotive SoCs could mean the difference between components that perform well for the expected lifespan and those that fail earlier than anticipated. Achieving a level of chip robustness involves avoiding service failures that are more frequent and/or more severe than acceptable.
Reliability is impacted by process/voltage variability; wear-out failures stemming from factors such as aging, thermal effects, electromigration (EM), and electrostatic discharge (ESD); and random failures due to environmental issues such as power surges. One of the key automotive industry standards addressing reliability, along with longevity, comes from the Automotive Electronics Council: AEC-Q100. AEC-Q100 provides failure mechanism-based stress test qualification for packaged automotive ICs. Given that automotive chips must operate under harsh conditions, stress testing while they are being designed can lead to more reliable automotive systems.
Many of the issues that impact SoC reliability require innovation to analyze and fix at the SoC level, with coverage for all paths. Device aging must be analyzed according to the stress temperature, stress voltage, lifetime, and signal probability of the SoC, otherwise known as the “mission profile.” A static timing analysis- (STA-) based solution that covers all paths in the design and provides high accuracy with the low cost of library characterization enables the analysis to be performed for comprehensive mission profiles. Automated design robustness analysis and optimization technology that can identify cells that are susceptible to process variation, or paths that are susceptible to voltage variation, are crucial to prevent timing failures.
Signal and cell-level EM is another challenging consideration. For automotive reliability, the design must meet signal EM requirements (average, RMS, and peak current) as specified by the semiconductor process foundry. EM analysis involves accurate modeling, extraction, and calculation of current through wires in the design. In addition to signal EM rules, cells must be used under reliable conditions to not exceed the maximum frequency or toggle rate. As such, cell-level EM must be modeled during library characterization to record the maximum frequency for different slew and load conditions. Signal EM violations must be fixed during optimization in physical implementation. Cell-level EM violations must be fixed during ECO by replacing cells to meet EM requirements.
During the SoC’s in-field operation, employing silicon lifecycle management (SLM) techniques can extend its lifetime. On-chip path margin monitoring (PMM) can be implemented to reduce the operating voltage for targeted performance profiles. Reducing the operating voltage offers the benefit of reducing voltage and temperature stress on devices, which increases the SoC’s lifetime. Continuous path-margin monitoring provides analytics to optimize the SoC’s performance.