Boost SoC Performance with PCIe PIPE 4.4.1

VIP Expert

Jan 16, 2018 / 2 min read

PCIe is a multi-layered serial bus protocol which implements dual-simplex link. It provides high speed data transfer and low latency owing to its dedicated point to point topology. To accelerate verification and device development time for PCIe based sub-systems, PIPE (PHY Interface for the PCI Express) architecture was defined by Intel. PIPE is a standard interface defined between PHY sub-layer (PCS – Physical Coding sub-layer) and MAC (Media Access Layer).

The first stable version of PIPE was published as PIPE 2.0 in 2007. Over the time, PIPE has evolved to support higher speeds and the added functionalities of next generation PCIe specifications. PIPE 4.4.1 specification, released in early 2017, is fully compliant with PCIe 4.0 base specification supporting 16GT/s speed. It has major improvements over PIPE 4.3, while maintaining backward compatibility. Following diagram illustrates PIPE interface, and the partitioning of PHY layer of PCIe.

pipe architecture diagram

The following list summarizes the newly added/modified features in PIPE 4.4.1 over PIPE 4.3.

  1. Nominal Empty elastic buffer mode: Provides better optimization in data flow with smaller worst case and average latency compared to the Nominal Half Full elastic buffer mode.
  2. Rx Margining with introduction of Message Bus Interface: Provides a way to initiate and participate in non-latency sensitive PIPE operations using a small number of wires. It also enables just released PIPE 5.0 operations to be performed without adding additional wires/signals.
  3. SRIS: Provides a way to indicate PHY about the Separate Refclk Independent SSC architecture support.
  4. Gen4 Equalization between MAC and local PHY: Provides dedicated controls for Gen4 Equalization over Gen3 Equalization.
  5. L1 sub-state power management: Provides ultra-low power operations with introduction of RxEiDetectDisable and TxCommonModeDisable signals.
  6. TxCompliance and TxElecIdle signals sampling mechanism.
pipe 4

Synopsys VC VIP for PCIe supports all the features of PIPE starting from v2.0 to v4.4.1. The VIP provides robust protocol checkers that flag specification violations to catch complex bugs. It simplifies the verification of PCIe protocol with different types of complex configurations. Synopsys is engaged with the early adopters of PCIe Gen5 Verification IP and testsuite also, based on version 0.5 of the specification. PCIe Gen5 VIP and testsuite are available as part of the 2017.12 release of VC VIP product. Read our recent blog on PCIe Gen5 – Is Your Design PCIe Gen5 Ready? Verify with Synopsys VIP and Testsuite.

The upcoming PCIe blogs will introduce PIPE 5.0 and expand further on features of PCIe Gen5, Gen4, and PIPE 4.4.1, so stay tuned. To know more about Synopsys PCIe and other VIPs please visit

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