As an industry leader and pioneer of the EDA industry, standards are part of our DNA at Synopsys. We aren’t just involved with shaping the standards and providing quality IP, but also actively educating customers on different complexities that need to be addressed to implement the latest standards on chips.
To achieve the lowest latency with maximum throughput for all transfer sizes, we work closely with several industry bodies to propel technology advancements forward and enable our customers to meet their performance and data connectivity requirements. Synopsys has been a long-time member of IEEE and is active in many industry standards groups, including PCI-SIG, IEEE, The Ethernet Consortium, Accellera, to list a few.
Our significant investment in developing silicon-proven and standards-compliant IP on the most advanced process technologies has provided designers with a low-risk path to achieving their design requirements. Tools like the Synopsys RTL Architect™ enable RTL designers to “shift-left” and predict the implementation impact of their RTL changes faster than ever before.
Synopsys IP solutions have gone through extensive third-party interoperability testing and certification, enabling SoC designers to accelerate time-to-market and reduce integration risk for next-generation SoCs. In May 2021, we acquired MorethanIP, a provider of Ethernet Digital Controller IP supporting data rates up to 800G. The acquisition expanded our silicon-proven high-speed Ethernet IP portfolio with an integrated 200G, 400G and 800G MAC, PCS and PHY offering, allowing designers to meet their interoperability expectations and have access to a team of experienced R&D engineers who have led the development of the high-speed Ethernet specification. In fact, Synopsys MorethanIP team worked closely to define the Ethernet Technology Consortium’s latest 800 GbE standard.
In addition, the IEEE-compliant Synopsys DesignWare® Ethernet IP Solutions ensure interoperability between digital and mixed-signal layers and are extremely low in power, area, and latency for applications such as automotive, consumer, high-performance computing, and networking. To strengthen our HPC IP portfolio even further, we announced the industry’s first controller, PHY, and verification IP solutions for PCIe 6.0 technology, supporting the latest features including 64 GT/s PAM-4 signaling, FLIT mode, and L0p power state.
Going forward, our vision is to advance the entire electronic design industry with access to the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing.