IP is an important part of the equation for Ethernet connectivity that ensures first-pass silicon success. A MAC+PCS+PHY integrated Ethernet IP can support increasing bandwidth and data rate requirements, low-latency needs, and interoperability expectations.
Addressing the challenges, Synopsys provides the industry’s only complete 200G/400G/800G Ethernet IP solution. The Synopsys DesignWare® Ethernet Controller IP portfolio for 200G/400G and 800G Ethernet complements our 112G/56G Ethernet PHY IP solutions in advanced FinFET processes, which enables Ethernet interconnects up to 800G. The resulting low-latency, high-performance Ethernet IP solution is ideal for networking, AI, and high-performance computing SoCs.
DesignWare Ethernet IP Solutions are IEEE-compliant and have undergone extensive third-party interoperability testing and certification, reducing integration risks, accelerating time-to-market, and enabling you to focus on product differentiation. The portfolio includes:
- Configurable controllers and silicon-proven PHYs for speeds up to 400G/800G
- Verification IP
- Software Development Kits
- Interface IP subsystems
Once an Ethernet-based design has been developed, of course, it must be verified. This is where Synopsys VC Verification IP (VIP) for Ethernet 800G can help accelerate verification closure, providing a comprehensive set of protocol, methodology, verification, and productivity features. Implemented in native SystemVerilog and UVM, VC VIP runs natively on all simulators and can be integrated, configured, and customized with minimal effort. In addition, source code UNH-IOL test suites are available for key Ethernet features and clauses, allowing teams to quickly jumpstart their own custom testing and accelerate verification closure.