GUC Leverages 3DIC Compiler to Enable 2.5D/3D Multi-Die Package

Synopsys Editorial Staff, WeiHsun Liao

Jun 12, 2024 / 5 min read

WeiHsun is a guest author and Deputy Manager, Core Methodology Department, at Global Unichip Corp.

In the rapidly evolving world of ASIC design, the shift from monolithic to 2.5D and 3D multi-die architectures represents a significant leap forward. This approach, which integrates multiple chiplets (also knowns as dies) into a single package, demands not only a new level of IC design innovation but also an increased complexity in coordination and integration. At the forefront of this technological revolution is Global Unichip Corp. (GUC), which has effectively harnessed the power of Synopsys’ 3DIC Compiler, a unified exploration-to-signoff platform, to streamline its chip design processes and reduce overall cycle time.

GUC recently presented their multi-die tape-outs at SNUG Silicon Valley 2024, which were made more efficient by Synopsys’ 3DIC Compiler through the implementation of die floorplanning and related bump assignments. 3DIC Compiler helped further check the physical and logical connectivity, sync up information from die to die quickly, and, ultimately, shorten chip design cycle timelines for GUC’s 2.5 and 3D CoWoS designs.

3dic design multi-die chips

2.5D and 3D IC Design Challenges

This distinction between 2.5D and 3D IC design approaches becomes critical in addressing the increasing demand for higher performance and more integrated systems. Each method comes with its unique set of challenges and benefits, tailored to specific application needs.

3dic design tools

2.5D and 3D design typically involves using an interposer, such as Chip-on-Wafer-on-Substrate (CoWoS), which enables the connection of silicon dies to a substrate via microbumps and C4 bumps, along with Through-Silicon Vias (TSVs). This architecture supports heterogeneous integration and the assembly of chiplets to achieve high memory bandwidth. However, it also introduces several challenges:

  • Interposer Constraints: As interposers grow larger, managing their size becomes a critical design challenge. The larger the interposer, the more complex the thermal and mechanical stresses it must withstand, which can lead to issues such as bump cracking.
  • Cross-Die Connectivity: Effective cross-die bump assignment is essential for maintaining IR quality and reducing assembly issues. Microbump locations need to be determined early in the design process to avoid iterative updates, and robust die-to-die routing patterns are necessary to meet performance specifications.
  • Power and Signal Integrity: High-power designs require interposer embedded Deep Trench Capacitors (eDTC) for enhanced signal integrity (SI) and power integrity (PI) performance. SI/PI simulation is time-consuming and needs to ensure that all channels are balanced.

Conversely, 3D design strategies, such as System on Integrated Chips (SoICs), involve stacking chips directly using hybrid bonding. This stacking method differs significantly from 2.5D design as it utilizes hybrid bonding, allowing for a smaller chip size, better yield, and productivity. Key challenges include:

  • Hybrid Bonding Specifics: Managing die-to-die interface and ensuring precise hybrid-bond assignments are crucial for 3D designs. This includes addressing cross-die hierarchical block standing and flip alignment within 3D hierarchical designs.
  • Thermal and Power Management: 3D stacking introduces complex issues in power planning and thermal management. Effective strategies for IR/EM signoff, power consumption, and TSV number/pitch estimation are vital. Additionally, 3D stacking requires detailed thermal analysis to prevent overheating.
  • Signal and Power Routing: Co-design of power/ground and signal hybrid bonds is necessary to ensure integrity and performance across the stacked dies. This also includes cross-die coupling extraction and accommodating process variations in 3D stacking static timing analysis (STA).
  • Design for Testability (DFT): Implementing a DFT scan scheme that adequately detects faults across stacked dies is another critical aspect of 3D design, as is ensuring robust process variation checks and layout verifications (DRC/LVS/3D-stacking checks).

3DIC Compiler: Key Capabilities and Innovations

The choice between 2.5D and 3D design approaches depends largely on the specific application requirements, including size, performance, and integration complexity. The 3DIC Compiler from Synopsys provides a suite of tools in a unified platform that empowers GUC to handle various critical aspects of multi-die system design:

  • Automated and Optimized Routing: With the 3DIC Compiler’s auto-router, GUC has achieved a 50% reduction in implementation time for HBM3 signal routing while meeting a 7.2Gbps performance target. This efficiency is further enhanced by GUC’s in-house expertise in power grid tuning, signal shielding optimization, and SI verification.
3dic routing
  • Effective Design Management: The platform maintains rigorous control over each chiplet design specification, simplifying version control and the management of design databases, libraries, technology files, and constraint files. This streamlined management is crucial for maintaining consistency and accuracy across complex projects.
  • Advanced Verification and Integration: Integration of 3Dblox with the 3DIC Compiler facilitates more efficient cross-die RC extraction, STA, and physical verification. This integration ensures that each stage of the design aligns with the signoff requirements, enhancing the reliability of the final product.
ic design verification
  • Addressing Bump Misalignment: The 3DIC Compiler can aid designers by providing a system-level 3D view, facilitating multi-die block partitioning and TSV/bump co-design and significantly reducing bump misalignment issues.

Transforming Chip Design Processes and Reducing Time to Market

The 3DIC Compiler features listed above translate directly into time saving and optimization benefits that GUC directly experienced. 

“GUC’s use of the Synopsys 3DIC Compiler platform has not only optimized its design and validation processes but also significantly accelerated its time to market for multi-die packages,” said WeiHsun Liao, Deputy Manager at GUC. “By automating routing, which led to 50% reduction in implementation time, and incorporating powerful signoff tools, GUC can focus more on innovation and productivity, rather than on addressing iterative design challenges.”

As the semiconductor industry progresses toward more sophisticated and integrated solutions, platforms like Synopsys’ 3DIC Compiler become indispensable in managing increased complexity and ensuring the success of next-generation multi-die packages. By addressing these challenges with 3DIC Compiler, GUC continues to lead in the creation of advanced multi-die packages, showcasing the potential of both 2.5D and 3D technologies in overcoming modern electronic design hurdles.

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