Unique AMS EmulationTechnology

Interview wtih Dr. Johannes Stahl and Dale Donchin

Ian Land, senior director of aerospace and government marketing sat down with Dr. Johannes Stahl, senior product marketing director, and Dale Donchin, aerospace and government senior program manager, to learn more about our collaboration with DARPA and other partners to develop one-of-a-kind error free silicon verification capability.

 


Q1. What is AMS emulation technology?

Dr. Johannes Stahl

Semiconductor device technology is typically digital or analog, or a combination of the two, referred to as AMS for analog mixed-signal. Emulation is the ability to test a semiconductor device on a specialized hardware platform before the design is complete. This is becoming a critical step for error-free silicon designs. Historically, suppliers like Synopsys have had digital emulation but not AMS emulation. So, Synopsys teamed with DARPA and other partners to develop this one-of-a-kind technology.

Figure 1: The ZS4 class of ZeBu emulators


Q2. What motivated DARPA to develop and sponsor this initiative?

Dale Donchin

DARPA is investing to improve the design and verification of semiconductors and the speed of EDA innovation. As Johannes mentioned, AMS emulation is one of those opportunity areas due to the increasing complexity of semiconductor devices that often include the combination of analog and digital circuits.


Q3. What was Synopsys’ role?

Dale Donchin

Synopsys took on the challenge of high-speed AMS system verification performance that has been falling the exponential advancements observed in Moore’s Law. The industry norm of using SPICE was unable to keep pace against increasingly more complex circuits, Synopsys took on the challenge of high-speed AMS system verification performance that has been falling the exponential advancements observed in Moore’s Law. The industry norm of using SPICE was unable to keep pace against increasingly more complex circuits, couldn’t provide sufficient capacity for system-level designs, and lacked the ability to co-simulate with system software.  A completely different approach was necessary: Synopsys worked to build virtual models of semiconductor chips that enabled AMS verification prior to silicon tapeout.

Figure 2: Adapting AMS content to emulation


Q4. Why is this important to Aerospace and Defense?

Dale Donchin

The A&D community suffers from significant cost and schedule overruns when design flaws are detected post-silicon manufacturing.  However, until now, it was challenging, if not impossible to verify, pre-silicon, a complete system encompassing AMS content like DDR and SERDES physical interfaces, digital processors, and firmware required to calibrate, tune, or equalize the high-speed analog circuits with real-world varying phenomena such as PCB impedance.

Figure 3: Modern-day SoC with many AMS components


Q5. How did Synopsys overcome the challenge of pre-silicon verification for AMS designs?

Dr. Johannes Stahl

Synopsys capitalized on the existing SystemVerilog Real Number Model (RNM) standard for capturing analog circuit behavior and interfaces to digital logic. This is already used on simulation, but the execution speed was insufficient.   RNMs support floating point signal values common in analog designs, using mathematical equations to express circuit behavior with a high degree of fidelity.  Resolution functions describe the conversion between analog and digital signal domains.  RNMs are generic, enabling their use for a wide range of AMS designs, both as inputs to and outputs from a digital-based subsystem.  Using an established and well-documented hardware description language was preferred over proposing another syntax.

Synopsys enhanced its emulation technology to enable AMS emulation as part of its high-performance architecture. RNM models can now be mapped as part of emulation.


Q6. What results did users achieve?

Dr. Johannes Stahl

A recent example is the verification of a system using DDR memory. The system driver must perform a complex series of operations to train the system setup for the “sweet spot” where the best signal-to-noise-ration for the analog eye diagram is reached. A performance increase of 200x for this emulation of the firmware behavior compared to using simulation was observed. The entire system, including the DDR controller, PHY, memory models, processor, and calibration software, can be verified pre-silicon, significantly reducing system integration risks and deployment time.


Q7. How can this accomplishment be utilized?

Dr. Johannes Stahl

The advent of multi-die system integration is a tidal change in the way the semiconductor industry needs to approach system validation. Tasks that could traditionally happen at the board level post-silicon now have to move to pre-silicon. We expect that many design teams will enhance their verification methods to include AMS emulation to verify the many die-to-die interconnects. 


Q8. What’s next for the aerospace and defense market with this technology?

Dale Donchin

Pre-silicon system level validation of DDR IP is only one instance benefitting from AMS Emulation. Similarly, complex AMS designs like PCIe, power conditioners, filters, converters, and many types of sensors can be verified in the system context using AMS Emulation. 

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