Pre-Instrumented for Performance and Power Analysis in Platform Architect
- Traffic Generators
- Interconnect Models
- Memory Subsystem Models
- Processor Models
Synopsys Platform Architect™ Ultra supports the broadest commercially available portfolio of pre-instrumented SystemC™ TLM models for SoC architecture exploration and validation. Synopsys Architecture Design Models enable architects and system designers to efficiently design, analyze, and optimize the performance, power and cost of multicore SoC architectures in Platform Architect.
The library contains SystemC TLM models of commonly required architectural components including generic traffic generators, interconnects, memory subsystems, and embedded processors, including:
- Generic Virtual Processing Unit (VPU) supports task-driven and trace-driven traffic generation
- Generic approximately-timed SystemC TLM bus libraries for coherent and non-coherent protocols including AMBA 4 AXI™, ACE™, and CHI™ protocols
- Cycle-accurate SystemC TLM bus libraries for Arm AMBA® 2 AHB™/APB™, AMBA 3 AXI™, and AMBA 4 AXI™ protocols, including models for ARM CoreLink™ Network Interconnect and Synopsys DesignWare IP solutions for AMBA
- Approximately-timed models available from Arteris® for the Arteris FlexNoC™ Network on Chip (NoC) interconnect, which provide on-chip connectivity for AMBA® AXI™, AHB™, AHB-Lite, APB™, and PIF protocols
- Integration of Arm Cycle Models of Arm System IP, like Arm CoreLink CMN600, CCI550, MMU600, etc.
- Integration of in-house bus libraries for usage in Platform Architect Ultra
Memory Subsystem Models
- Generic approximately-timed SystemC TLM memory subsystem models for Arm AXI and IEEE-1666 2011 SystemC TLM-2.0 interfaces
- Accurate SystemC TLM memory subsystem models of the Synopsys DesignWare® DDR5/4 Controller, LPDDR5/4/4X Controller, and Enhanced Universal DDR Memory Controller (uMCTL2)
- Cycle-accurate memory subsystem models are available for Platform Architect through HDL co-simulation with user-provided, third-party and Synopsys RTL memory controller IP
- Integration of Arm Cycle Models of Arm Processor IP from Arm Cortex-A, Cortex-R, and Cortex-M families
- Cycle-accurate SystemC TLM processor models are available for Synopsys ARC, Tensilica and CEVA processor families, and through HDL co-simulation
Developed in partnership with leading IP providers including Synopsys ARC, Arm, Tensilica, and CEVA; these models are configurable and fully instrumented for architecture analysis. In addition, see the DesignWare TLM Library and Virtual Prototyping Models pages for more models that are compatible with our Architecture Design solution. Synopsys can also work with customers to create architecture models through our CoStart Enablement Services.