Advanced geometry nodes such as FinFET pose significant design and manufacturing challenges that impact some implementation tools. In particular, complex multi-patterning lithography requirements involve:
- Rule-aware placement and routing to ensure ability to color masks correctly and efficiently
- In-Design physical verification throughout the flow to reduce time-consuming, uncertain iterations
- Accurate higher levels of extraction and timing analysis to allow for manufacturing variability
Advanced geometry nodes will enable designs to run at a multi-GHz+ operating frequency. In order to achieve this, improved modeling, guidance and analysis should be handled by the tools with high degrees of predictability throughout the design flow. Size and performance requirements for next-generation designs require higher levels of capacity, enhanced multi-core processing for faster runtime and an integrated design environment to maximize design productivity. Synopsys’ comprehensive, foundry-certified advanced geometry solution provides the following features that help designs make it to market faster:
- Early RTL design exploration and block feasibility analysis
- Physical guidance from synthesis to place and route
- Digital and Custom co-design for advanced mixed-signal requirements
- In-Design physical verification with automatic detection and repair of complex design rules
- Tightly-coupled extraction and signoff capabilities with implementation tools
- Physical ECO guidance and leakage recovery capabilities from signoff analysis
