Silicon and Production-Proven FinFET Solution

Synopsys' Galaxy Design Platform Enables 90% of Volume-Production FinFET Designs

Enabling Next-generation Silicon Designs

Synopsys has a proven track record for delivering the leading solutions targeting the most advanced process nodes. In collaboration with IDMs, foundries and academia, Synopsys delivers the industry’s most comprehensive and effective FinFET solutions. Most of the world’s FinFET devices are designed with Synopsys TCAD tools; Synopsys has the broadest portfolio of silicon-proven IP for FinFET, and more than 90% of the leading volume-production SoCs have been designed with the Galaxy™ Design Platform. Synopsys’ new Custom Compiler™ visually-assisted custom layout solution is tuned for rapid implementation, shortening the time it takes to complete FinFET custom design tasks from days to hours.


  • Broadest silicon-proven FinFET-ready EDA solution spanning Process development, SPICE design Implementation and IP
  • Earliest collaboration with foundries and academia for development of latest models and process development and certification
  • Comprehensive solution for the new challenges, such as double-patterning and 3-D transistors, introduced by 20nm planar and 16/14nm and below FinFET manufacturing rules with 3D-IC integration
  • Minimizes impact to existing methodology with transparent adoption, easing transition to advanced process technologies
  • Complete foundry-certified solutions for IC Design, Implementation and Signoff for correct first-time silicon


Design Challenges

16/14nm and below FinFET and 20nm advanced geometry nodes pose significant design and manufacturing challenges that impact some implementation tools. In particular, complex double patterning lithography requirements involve:

  • Rule-aware placement and routing to ensure ability to color masks correctly and efficiently
  • In-Design physical verification throughout the flow to reduce time-consuming, uncertain iterations
  • Accurate higher levels of extraction and timing analysis to allow for manufacturing variability

Advanced geometry nodes will enable designs to run at a multi-GHz+ operating frequency. In order to achieve this, improved modeling, guidance and analysis should be handled by the tools with high degrees of predictability throughout the design flow. Size and performance requirements for next-generation designs require higher levels of capacity, enhanced multi-core processing for faster runtime and an integrated design environment to maximize design productivity. Synopsys’ comprehensive, foundry-certified advanced geometry solution provides the following features that help designs make it to market faster:

  • Early RTL design exploration and block feasibility analysis
  • Physical guidance from synthesis to place and route
  • Digital and Custom co-design for advanced mixed-signal requirements
  • In-Design physical verification with automatic detection and repair of complex design rules
  • Tightly-coupled extraction and signoff capabilities with implementation tools
  • Physical ECO guidance and leakage recovery capabilities from signoff analysis

Foundry Partners and Consortiums

Synopsys is actively working with leading foundries, consortiums and eco-system partners to address the significant challenges of advanced FinFET process technologies. This results in availability of foundry certified solutions in the shortest possible time.