- All Products
- Software Integrity
- Semiconductor IP
- Verification
- Design
- Silicon Engineering
- Application Security Services
- Dynamic Analysis (DAST)
- Mobile Application Security
- Penetration Testing
- Managed Static Analysis
- All Services
- Software Security
- Silicon Design
- Community
- About Us
< All Products
< All Products
< All Products
< All Products
< All Products
< All Products
< overview
All Products
+ Software Integrity + Semiconductor IP + Verification + Design + Silicon Engineering + Optical Solutions< Software Integrity
< Software Integrity
Application Security Services
Dynamic Analysis (DAST) Mobile Application Security Penetration Testing Managed Static Analysis< Software Integrity
< Software Integrity
< Software Integrity
Blog
< Software Integrity
Support
< overview
Software Integrity
+ Application Security Products + Application Security Services + Resources + Training & Education Blog Support< Semiconductor IP
< Semiconductor IP
Memories & Libraries
Logic Libraries Memory Compliers Duet Packages HPC Design Kit Embedded Test & Repair Non-Volatile Memory< Semiconductor IP
< Semiconductor IP
Processor Solutions
ARC Processors Embedded Vision Processors Development Tools Operating Systems Ecosystems ASIP Tools< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< overview
< Verification
< Verification
< Verification
< Design
< Design
< Design
< overview
< Silicon Engineering
< overview
< main menu
< Solutions
< Solutions
Industry Solutions
Automotive Cloud Computing Financial Services Industrial Controls Systems Healthcare< Solutions
< overview
< All Services
< All Services
< All Services
< overview
< Software Security
< Software Security
Managed Services
< Software Security
Program Development & Design
Maturity Model (BSIMM) Maturity Action Plan (MAP) Policies & Standards Security Metrics Software Security-in-a-Box< Software Security
< Software Security
Support
< overview
Software Security
+ Software Security Services Managed Services + Program Development & Design + Training Support< Silicon Design
< Silicon Design
< Silicon Design
< Silicon Design
< main menu
< Community
< Community
< Community
< Community
Interoperability
ARC Access HAPS Connect HSPICE Integrator In-Sync System-Level Catalyst TAP-in VC Apps Access< Community
< Community
< Community
< overview
Community
+ Community + SNUG + Partners + Interoperability + Academic Programs + Company Blogs + BSIMM< About Us
< About Us
< About Us
< About Us
< About Us
Silicon and Production-Proven FinFET Solution
Synopsys' Galaxy Design Platform Enables 90% of Volume-Production FinFET Designs
Enabling Next-generation Silicon Designs
Synopsys has a proven track record for delivering the leading solutions targeting the most advanced process nodes. In collaboration with IDMs, foundries and academia, Synopsys delivers the industry’s most comprehensive and effective FinFET solutions. Most of the world’s FinFET devices are designed with Synopsys TCAD tools; Synopsys has the broadest portfolio of silicon-proven IP for FinFET, and more than 90% of the leading volume-production SoCs have been designed with the Galaxy™ Design Platform. Synopsys’ new Custom Compiler™ visually-assisted custom layout solution is tuned for rapid implementation, shortening the time it takes to complete FinFET custom design tasks from days to hours.
Benefits
- Broadest silicon-proven FinFET-ready EDA solution spanning Process development, SPICE design Implementation and IP
- Earliest collaboration with foundries and academia for development of latest models and process development and certification
- Comprehensive solution for the new challenges, such as double-patterning and 3-D transistors, introduced by 20nm planar and 16/14nm and below FinFET manufacturing rules with 3D-IC integration
- Minimizes impact to existing methodology with transparent adoption, easing transition to advanced process technologies
- Complete foundry-certified solutions for IC Design, Implementation and Signoff for correct first-time silicon
Design Challenges
Advanced geometry nodes such as FinFET pose significant design and manufacturing challenges that impact some implementation tools. In particular, complex multi-patterning lithography requirements involve:
- Rule-aware placement and routing to ensure ability to color masks correctly and efficiently
- In-Design physical verification throughout the flow to reduce time-consuming, uncertain iterations
- Accurate higher levels of extraction and timing analysis to allow for manufacturing variability
Advanced geometry nodes will enable designs to run at a multi-GHz+ operating frequency. In order to achieve this, improved modeling, guidance and analysis should be handled by the tools with high degrees of predictability throughout the design flow. Size and performance requirements for next-generation designs require higher levels of capacity, enhanced multi-core processing for faster runtime and an integrated design environment to maximize design productivity. Synopsys’ comprehensive, foundry-certified advanced geometry solution provides the following features that help designs make it to market faster:
- Early RTL design exploration and block feasibility analysis
- Physical guidance from synthesis to place and route
- Digital and Custom co-design for advanced mixed-signal requirements
- In-Design physical verification with automatic detection and repair of complex design rules
- Tightly-coupled extraction and signoff capabilities with implementation tools
- Physical ECO guidance and leakage recovery capabilities from signoff analysis
Foundry Partners and Consortiums
Synopsys is actively working with leading foundries, consortiums and eco-system partners to address the significant challenges of advanced FinFET process technologies. This results in availability of foundry certified solutions in the shortest possible time.