Efficient Top-Level Interconnect Planning and Implementation with Synopsys IC Compiler II

Efficient Top-Level Interconnect Planning and Implementation with Synopsys IC Compiler II

Jiangtao Meng, Sr. R&D Manager at Synopsys, discusses how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning (TIP) technology, to accelerate project schedules while achieving the highest performance targets that the most challenging semiconductor segments such as AI and HPC demand.