1:1 with Charlie Matar

We sat down with Charles Matar, Senior Vice President of System Solutions & Ecosystem Enablement Group, to learn more about the current needs of the semiconductor market for higher levels of integration and performance and how multi-die integration in a package may address them. Prior to joining Synopsys, Mr. Matar was Vice President of North America for TSMC responsible for engineering support teams driving advanced and mainstream process technologies, RF, analog, and design enablement for the high-performance computing, mobile, IoT and automotive market segments. He has also led global engineering teams at Intel, AMD, and Qualcomm, both as a General Manager and a Vice President of Product Development.

Q: Hello Charlie, thanks for taking the time to speak with us today. Synopsys just announced a new solution for multi-die integration. What is multi-die integration and what has driven the need for this solution now?

Charlie Matar:

It’s great to be here; thanks for having me. Yes, we launched 3DIC Compiler, the industry’s first unified packaging platform that enables higher levels of 2.5D/3D multi-die integration.   The need for such a packaging solution is driven by different markets like mobile, machine learning (ML), artificial intelligence (AI), high-end networking, and high-performance computing (HPC) applications. In addition, with the continuous demand for increased compute, IO, memory bandwidth, IP reuse, lower product cost requirements and the slow down of Moore’s law, 2.5D & 3D packages provide the system level architecture to address these challenges.

Q: Is Moore’s law running out of gas? Can you elaborate on why multi-die integration in a package is an attractive solution to putting more gas in Moore’s tank?

Charlie Matar:

As Moore’s law is slowing down, resulting technology scaling and transistor/wafer cost are not keeping pace with the ever-growing needs for more performance and lower cost. This is where heterogeneous architectures are becoming ubiquitous, especially in HPC applications. With that comes the need for 3DIC Compiler’s multi-die integration capabilities to maintain performance, power, and cost curves. 

Q: Why are today’s packaging tools and solutions not sufficient to solve the design engineer’s challenges with multi-die designs?

Charlie Matar:

Many of our customers are realizing that the package design tools that they have been using are running out of bandwidth and cannot address the complexities of the multi-die designs. Many of their packaging tools are MS Windows-based, lack automation and have databased size limitations. Each has its own interface and use models that do not allow cross-discipline collaborations that are required for today’s complex multi-die designs.

Furthermore, packaging tools suffer from a lack of holistic integrated solutions for power, electrical and thermal analysis. With 3DIC Compiler, we provide a fully integrated solution under one cockpit to serve as a single tool for design, analysis, and signoff for multi-die integration in a package. 

Q: What have we learned in working with our customers about multi-die integration enablement that has driven Synopsys to launch the 3DIC Compiler?

Charlie Matar:

We have been working very closely with our customers and partners since early 2010 to accelerate the development of 3DIC technologies and what we have learned first and foremost, is that co-design is a must for the success of the complex multi-die packages. With our silicon-proven finite-element method for modeling through-silicon-vias (TSV), 3DIC Compiler with its in-design extraction and physical verification, coupled with tightly integrated system-level signal, power, thermal and noise-aware optimization meets today’s market needs. 

Q: You say that 3DIC Compiler can improve user productivity and design quality, but does that only apply to advanced node designs? What about older nodes? Can the user combine dies from different foundries and technology nodes in a package?

Charlie Matar:

3DIC Compiler is both process and foundry agnostic. It supports heterogeneous integration in a package, by supporting multiple technologies.

Q: What kind of market segments will be looking to leverage multi-die integration? Automotive, HPC, IoT, AI?

Charlie Matar:

We are seeing an increasing trend at many leading market verticals, such as mobile, hyperscalers, AI and high-performance computing, to pursue multi-die integration in a package. This trend is driven by a need to optimize system-level performance as well as return-on-investment sensitivities in moving to the latest nodes. 

Q: Can you talk about what some of your first customers have had to say about the 3DIC Compiler?

Charlie Matar:

The early customer responses to 3DIC Compiler have been very positive with almost every discussion turning into an evaluation request. They are pleased to see a vendor that finally delivers a unified co-design platform that many had claimed to deliver in the past. 3DIC Compiler is setting a new standard in IC package design. 

Q: Thanks for your time, Charlie. Is there anything else you would like to add?

Charlie Matar:

You are welcome! We are very excited about 3DIC Compiler. It is a game-changing product for multi-die integration in a package. We look forward to enabling many more customers to successfully build their products leveraging Synopsys 3DIC solution and being part of driving new disruptive technologies forward.