In this 7th video of the series, Kai Wang, Director of Engineering at Synopsys, discusses in-design electrical analysis, and why it is critical to use signoff engines to check and fix resistance, capacitance and electromigration issues during layout.
In this 6th video of the series, Kai Wang, Director of Engineering at Synopsys, discusses methodology innovation in early electrical analysis to reduce iterations, and bringing signoff tools into the design process to speed up analog design closure.
In this 5th video of the series, Kai Wang, Director of Engineering at Synopsys, explains the need of Monte Carlo to improve yield, and how designers use advanced features like variation scoping and sigma amplification to avoid costly MC simulations.
In this 4th video of the series, Kai Wang, Director of Engineering at Synopsys, explains how device aging effects are more prominent because of stringent operating conditions, and how Synopsys robust aging analysis helps in design for reliability.
In this 3rd video of the series, Kai Wang, Director of Engineering at Synopsys, introduces circuit checks and explains how designers avoid wasted simulation time by finding design and performance problems automatically in advance.
In this 2nd video of the series, Kai Wang, Director of Engineering at Synopsys, introduces analog fault simulation and explains how Synopsys TestMAX CustomFault enables full-chip functional safety and test coverage analysis.
In part I of this video series, Kai Wang, Director of Engineering at Synopsys, will highlight key technologies in Synopsys Custom Design Platform to address reliability challenges across the analog design cycle.
Soni Kapoor, Sr. Technical Marketing Manager in Synopsys’ AMS Design Group, discusses Custom Compiler’s Visually-Assisted Layout Automation technology in action as we finish an analog block in one hour that took three days to complete the old-fashioned way.
Manu Pillai, Sr. Staff Applications Engineer at Synopsys, discusses common Analog / RF simulation challenges and how FineSim SPICE, an integral part of the Synopsys Custom Design Platform, can help address those challenges.
Neel Gopalan, Principal Applications Engineer in Synopsys' Custom Design Group, discusses how Custom Compiler’s Quick Start Kits (QSKs) help designers accelerate layout and reduce design iterations.
Michael Lynch, R&D Director for SerDes IP in Synopsys' Solutions Group, discusses how using Custom Compiler’s Partial Layout Extraction flow significantly reduces design iterations via early electrical analysis.
Custom Compiler speeds layout creation with user-guided routing and reusable templates.