Cloud native EDA tools & pre-optimized hardware platforms
The Synopsys Custom Design Family is fast, productive and easy to adopt. Thousands of analog and mixed-signal designers are using it daily to deliver new designs at an unprecedented pace. Below, some of the teams who have already made the move to Synopsys share their experiences.
This video discusses how CoreHW designed a fractional-N PLL IP with fundamental VCO frequency range of 19~20.25GHz with RF frequency range extended to 38~40.5GHz and 76~81GHz using the Synopsys Custom Design Family.
Watch how Samsung reduced the design iterations for their custom design flow by performing the EM analysis with foundry-qualified signoff engines during layout. Customers are also adopting this solution in their design flows through DSK (Design Solution Kit)..
This presentation highlights how Samsung Foundry adopted Synopsys Partial Layout Extraction (PLE) method for its advanced node 4, 5 and 7 nm designs and plans to implement it into its AMS ecosystem.
This presentation highlights how SK hynix achieved the benefits of using a template-based flow for design time reduction and 3x productivity gain on their analog layouts using Custom Compiler.
The proposed flow suits the new design structure by supporting the analog submodule replacement with SPICE. It provides more flexibilities for different test cases and provides more tool options. It also clearly defines the files that need to be maintained for digital and analog engineers.
Adria Bofill Petit, Co-founder and CTO of IMASENIC, discusses how IMASENIC develops CMOS image sensor products for a variety of applications and achieve first-time right designs for these complex sensors using Synopsys Custom Design Platform.
Hiroyuki Tsujikawa, Director of Technology Management Office at Panasonic Semiconductor Solutions, discusses Panasonic’s partnership with the Japanese government on the “Society 5.0” vision, which uses AI and IoT to meet social challenges. Panasonic’s work on this project includes development of highly accurate spatial and battery performance sensing devices for autonomous control. Panasonic deployed the Synopsys custom design platform to accelerate the design of these high precision analog devices.
Ashish Kumar, Sr. Manager, Memory IP division at STMicroelectronics India, discusses how ST uses the Sigma Amplification technology within CustomSim™ simulator to run 4+sigma Monte Carlo analysis on memory critical paths with far fewer samples than conventional approaches and thus ensure memory IP robustness in a cost effective manner.
Dino Toffolon, VP of Engineering for DesignWare®
IP at Synopsys, discusses his team's successful development of advanced, silicon-proven, mixed-signal interface IP using Synopsys Custom Design Platform.
Ken Evans, Managing Technologist at Seagate Technology, discusses the advantages of using Custom Compiler™ design and layout solution on their storage design.
At DAC 2018, Michael Dierickx discussed how Esperanto Technologies automated physical design of an energy-efficient machine-learning processor using Custom Compiler™ design and layout solution.
Hiroyuki Kobayashi, EDA Group Manager at Panasonic, discusses how he and his team improved automotive LSI layout productivity using Custom Compiler™ design and layout solution.