Ashish Kumar, Sr. Manager, Memory IP division at STMicroelectronics India, discusses how ST uses the Sigma Amplification technology within CustomSim™ simulator to run 4+sigma Monte Carlo analysis on memory critical paths with far fewer samples than conventional approaches and thus ensure memory IP robustness in a cost effective manner.
Dino Toffolon, VP of Engineering for DesignWare®
IP at Synopsys, discusses his team's successful development of advanced, silicon-proven, mixed-signal interface IP using Synopsys Custom Design Platform.
Ken Evans, Managing Technologist at Seagate Technology, discusses the advantages of using Custom Compiler™ design and layout solution on their storage design.
At DAC 2018, Michael Dierickx discussed how Esperanto Technologies automated physical design of an energy-efficient machine-learning processor using Custom Compiler™ design and layout solution.