Before defining physical synthesis, it is useful to define logic synthesis. Pioneered by Synopsys, logic synthesis takes as an input a description of a circuit expressed in a high-level language such as Verilog or VHDL. Other inputs include timing constraints for the design as well as the specific target implementation technology. Logic synthesis software then analyzes these inputs and maps them to a particular set of interconnected logic elements taken from cell libraries that are also provided as inputs to the process. Objectives of logic synthesis include optimization of timing, area, and power of the resultant design.
For many years, logic synthesis was a very effective method to design integrated circuits (ICs). The output of logic synthesis was then given to a place-and-route tool that would perform the necessary steps to physically implement the circuit in silicon. At advanced process nodes, however, this process breaks down. After placement and routing, the physical effects associated with wiring (e.g., increased signal delay and voltage drop) along with parasitic effects due to the proximity of certain devices cause the “physical” version of the circuit to behave differently than the “logical” version of the circuit. The result is many iterations between logic synthesis and place-and-route to achieve a working design.
Physical synthesis takes these implementation effects into consideration. An early floorplan of the design along with detailed routing estimates helps to provide early data on the previously mentioned physical effects. As a result, physical synthesis provides a convergent design flow that requires far fewer iterations.