Before defining physical synthesis, it is useful to define logic synthesis. Pioneered by Synopsys, logic synthesis takes as an input a description of a circuit expressed in a high-level language such as Verilog or VHDL. Other inputs include timing constraints for the design as well as the specific target implementation technology. Logic synthesis software then analyzes these inputs and maps them to a particular set of interconnected logic elements taken from cell libraries that are also provided as inputs to the process. Objectives of logic synthesis include optimization of timing, area, and power of the resultant design.

For many years, logic synthesis was a very effective method to design integrated circuits (ICs). The output of logic synthesis was then given to a place-and-route tool that would perform the necessary steps to physically implement the circuit in silicon. At advanced process nodes, however, this process breaks down. After placement and routing, the physical effects associated with wiring (e.g., increased signal delay and voltage drop) along with parasitic effects due to the proximity of certain devices cause the “physical” version of the circuit to behave differently than the “logical” version of the circuit. The result is many iterations between logic synthesis and place-and-route to achieve a working design.

Physical synthesis takes these implementation effects into consideration. An early floorplan of the design along with detailed routing estimates helps to provide early data on the previously mentioned physical effects. As a result, physical synthesis provides a convergent design flow that requires far fewer iterations.

How Does Physical Synthesis Work?

The overall goal of physical synthesis is to consider late-stage implementation effects early in the design process with sufficient detail to create a convergent design flow. Early design results then fit the requirements of late-stage implementation with minimal need for re-work. The general process of considering late-stage impacts earlier is called a shift-left approach.

In a physical synthesis design flow, an early floorplan of the design is developed for placement information, along with estimates of routing requirements based on this floorplan. State-of-the-art design flows use the same signoff-quality tools for these early phases. A unified data model that is shared by all tools in the flow makes this possible.

Based on these early estimates, more accurate wiring effects and placement-induced parasitics and congestion can be used during logic synthesis to ensure the resultant design will be closer to final requirements when physical implementation is done.

Importance of Physical Synthesis

The physical effects of wiring and placement in advanced technology nodes are substantial. If the delays and voltage drops induced by long wires are not considered during the synthesis phase, it becomes very difficult to achieve the power, performance, and area requirements of the chip. Many long design iterations between front-end and back-end design result, increasing design project costs and significantly extending the time required to complete the design.

Benefits of Physical Synthesis

The primary impact of physical synthesis is a predictable, convergent design flow where there is minimal need for re-work and correction as the design progresses from the front-end to back-end and tapeout. This convergent design flow allows the chip to be brought to market faster and with better quality. Faster time-to-market can have a substantial positive impact on the lifetime revenue of any advanced design project by opening the doors to potentially larger market share stemming from the early market lead. Improved product quality can also generate similar benefits.

Physical Synthesis and Synopsys

Synopsys Fusion Compiler™ delivers a singular RTL-to-GDSII digital implementation solution with a common data model.

Fusion Compiler provides an innovative RTL-to-GDSII flow that enables a new era in digital design implementation. The solution offers new levels of predictable quality-of-results to address the challenges presented by the industry’s most advanced designs. Its unified architecture shares technologies across the RTL-to-GDSII flow to enable a hyper-convergent design flow that delivers 20% better quality-of-results and 2x faster time-to-results.

Benefits of this technology include:

  • Single, integrated data model architecture for unmatched capacity, scalability, and productivity
  • Unified RTL-to-GDSII optimization engines that unlock new opportunities for best performance, power, and area results
  • Built-in signoff timing, parasitic extraction, and power analysis to eliminate design iterations
  • Pervasive parallelization with multi-threaded and distributed processing technologies for maximum throughput
  • Leading foundry process certified FinFET, gate-all-around, and multi-patterning aware design

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