Design a Time Interleaved ADC for 5G V2X Automotive Applications

August 30 - 31, 2021
A Virtual Experience 

Why Attend?

This 2-day virtual event is led by Professor Mohammed Ismail and Professor Mohammad Alhawari from the WINCAS Center of Excellence at Wayne State University. This event will be composed of lecture and lab sessions where analog design engineers will learn about the design, and verification of an ADC for 5G V2X (Vehicle-to-everything) application, using the GLOBALFOUNDRIES (GF) 22 nm FDSOI technology. Attendees will participate in hands-on lab sessions to learn about specific challenges related to ADC design such as designing the track-and-hold and comparator circuits, effects of timing skew on Time-Interleaved (TI) ADCs, and accounting for effects of post-layout parasitics as well as aging and statistical variation.

Who Should Attend?

This virtual experience is designed for:
  • Analog Design Engineers
  • Academic Luminaries 
  • University Students


Mohammed Ismail Chair & Professor, Electrical and Computer Engineering , Wayne State University 

Mohammad Alhawari Assistant Professor, Electrical and Computer Engineering, Wayne State University

Register Now


Lecture 1: 9:00 – 9:45 a.m. PT

  • Introduction to 5G in Automotive Applications
  • Introduction to GF 22 nm FDSOI Technology
  • TI SAR ADCs for multiband V2X applications  

Lecture 2: 9:45 – 10:00 a.m. PT

  • Design of the Track and Hold circuit

Lab 2: 10:00 – 10:45 a.m. PT

  • Track and Hold Simulation in SAR ADC

Lecture 3: 11:15 – 11:45 a.m. PT

  • Choosing capacitor types for DAC in Monotonic SAR ADC
  • Comparator design and kickback noise

Lab 3: 11:45 – 12:15 p.m. PT

  • Comparator kickback noise simulation

Lecture 4: 1:15 – 1:45 p.m. PT

  • Monotonic SAR Logic Design issues
  • Robustness of SAR ADC across all corners (loop delay)
  • SAR ADC Top level Design

Lab 4: 1:45 – 2:15 p.m. PT

  • SAR ADC Schematic Simulation (Getting the Metrics: SNDR, ENOB, SFDR, Power Consumption, …)
  • Corner Simulations

Lecture 5: 2:45 – 3:00 p.m. PT

  • Mitigation of Time skew in TI SAR ADC generated by MUX for V2X application (dummy circuits)

Lab 5: 3:00 – 3:15 p.m. PT

  • Simulation of time skew effect in TI SAR ADC

Lecture 1: 9:00 – 9:45 a.m. PT

  • Optimizing Digital Circuit Buffers driving capability according to DAC extracted parasitics
  • Layout challenges of SAR ADC

Lab 1: 9:45 – 10:15 a.m. PT

  • Parasitic extraction of DAC and post-layout simulation
  • DAC Linearity Simulation

Lecture 2: 10:45 – 11:15 a.m. PT

  • Design Constraints of TI ADC layout
  • Effect of timing mismatch

Lab 2: 11:15 – 11:45 a.m. PT

  • TI SAR ADC Simulation for minimizing the time skew error

Lab 3: 12:45 – 1:30 p.m. PT

  • Characterizing statistical variation in Comparator with Monte Carlo Simulation

Lecture 4: 2:00 – 2:30 p.m. PT

  • Effect of Aging in GF 22nm FDSOI
  • Effect of Electro-migration in GF 22nm FDSOI

Lab 4: 2:30 – 3:00 p.m. PT

  • Aging Simulation of Track and Hold
  • Electro-migration simulation of Comparator

Presented By


See You Virtually at ADCs for 5G V2X Automotive Applications!