A Simple Way to Use DesignWare Libraries in FPGA-Based Design Prototypes
By Angela Sutton, staff product marketing manager, FPGA Synthesis, Synopsys
Today, we are seeing more FPGA-based prototyping systems being used to verify huge ASIC designs. These designs typically consist of 1000s of source files and implement the equivalent of a multi-million gate ASIC. Often the design verification engineer who is implementing and verifying this design in an FPGA is not the one who authored the RTL code. Furthermore, there are usually multiple engineering teams involved with the project, resulting in constant revisions and frequent handing off of the RTL. With all these complexities, it is critical for hardware, software and verification teams to be able to maintain a single set of “Golden” source files that enables them to quickly and efficiently validate the RTL modifications made by the multiple teams and avoid potential pilot errors. Figure 1 shows the typical design hand-off process from the ASIC hardware team to the verification and software development teams.