Most of the same digital DesignWare IP cores including PCI E, USB 3.0, MIPI, DDR, SATA and HDMI, that you are using in your ASIC can be prototyped in an FPGA by using the coreConsultant software to configure the core and generate your normal ASIC RTL. Include this core’s RTL in your FPGA synthesis project, ready for synthesis and implementation in the prototype.
When prototyping an ASIC, the design verification and software development team will typically need to perform the following tasks:
- Controller + PHY interoperability validation
- System compliance testing
- Subsystem integration
- Early firmware and software development
The risk associated with the first two tasks of compliance testing and controller/PHY interoperability is significantly reduced when using the DesignWare cores with Synopsys’ HAPS® prototyping motherboards, since these tasks have already been performed before by Synopsys.
An example of the use of a DesignWare USB 3.0 core with the HAPS FPGA-based Prototyping Solution is shown in Figure 6.