Overcoming Data Converters Design Challenges with IP in FinFET Processes

By: Manuel Mota, Product Marketing Manager, Synopsys


The semiconductor industry continues to evolve to meet user demands for more features, performance, and battery life for less cost in each new generation of products for applications like mobile devices and digital homes. The evolution of the semiconductor process technology as captured by Moore’s law is the key enabler of such products. An important milestone for the industry was the transition from processes based on bulk, planar transistors to FinFET, tri-dimensional transistors. The transition enabled process technologies to continue to evolve for several more generations and deliver reduced feature size, high speed and low leakage.

Traditionally, the first products that are deployed in advanced process technologies implement overwhelmingly digital-centric data processing, whereas analog processing is kept in more conservative process technologies. Designers choose to leverage the more analog-friendly characteristics of the conservative processes, and mistakenly perceive that analog block area does not scale in advanced process technologies or can become expensive.

The evolution of technologies such as wireless connectivity with more than 10 Gbps data throughput per connection and device connectivity at a massive scale (100 billion links) requires more complex digital signal processing. For this reason, designers should consider the benefits of FinFET technology’s high-performance, low power and small area advantages. If the bulk of the analog functionality is integrated into a separate die, such as a RF chip, then it needs data converters – analog-to-digital (ADC) and digital-to-analog (DAC) – as the interface between the external analog processing functions and the internal digital processing blocks. Such data converters are typically integrated in the digital SoC to eliminate the need for additional power-intensive digital interfaces. Therefore, the need to deploy data converters in FinFET processes becomes paramount. This article describes how designers can overcome the challenges of data converter designs with IP for FinFET processes.

FinFET Processes for Data Converters Design

While there are challenges in designing data converters and other analog functions in FinFET processes, there are some key benefits that make it compelling to integrate such functions into SoCs in FinFET processes:

  • Enables the trend of integrating more functionality into the same SoC to continue
  • Lowers power by tightly integrating analog and digital functionality in the same SoC
  • Eliminates the need for power hungry chip-to-chip digital interfaces

Analog designers can also reap the benefits of the FinFET processes’ characteristics:

  • Reduced size of minimum features (line, transistor, etc.): Abundant inexpensive in area and high speed digital gates enable the implementation of digital-assisted analog functions to improve robustness and reduce IP area and power dissipation (for example, through digital calibration)
  • Better channel control: 3D gate extends the ability to control the device gate and improve the overall characteristics of the transistor, both when operating as a switch and as an analog, amplifier device
  • Faster devices: High speed process, with transistors having high transit frequency (Ft), removes certain design constrains for analog functions requiring very high bandwidth or high speed
  • Reduced device variability: Better device matching characteristics simplify analog design and enable area reduction

Layout vs Schematic in FinFET Design Flows

FinFET processes have specific characteristics that make the traditional design flows defined for planar CMOS designs ineffective. Analog designers must adapt their methodologies to take into account characteristics such as:

  • Discrete quantization of FinFET transistor sizes
  • High dependency of the electrical characteristics on the layout parasitics
  • Higher resistivity of metal lines and higher parasitic capacitances
  • Double patterning impact on matched structures

By creating parallel and series combinations of regularly dimensioned FinFET devices to achieve virtually any effective device width/length, some complex characteristics of FinFET processes like the finite granularity of the fin width can be effectively managed. Therefore, designers can design at a slightly higher level of abstraction (effective device) to reduce the complexity of the electrical design. Figure 1 shows a regularly dimensioned FinFET layout where individual transistors are the intersection of the vertical red lines (the polysilicon) and the horizontal blue lines (the fin) in regions that overlap with the green rectangles (active areas).

Figure 1: Illustration of a regular FinFET layout

Figure 1: Illustration of a regular FinFET layout

However, aging effects caused by Electromigration, increased negative-bias temperature instability (NBTI), and positive-bias temperature instability (PBTI) force the designer to assume higher design margins, sometimes at the expense of size or performance.

The complex dependency of the device’s electrical characteristics on the layout parasitic results in a very tight dependency of the circuit behavior on the physical layout. This means that the traditional analog design flow that relied on validating a finished circuit schematic, before moving it to layout, will be inefficient. The effect of layout parasitics cannot be easily recovered by small tweaks to the design, but rather may require a complete re-design of the electrical circuit.

A more efficient flow relies on the creation of physical layout of the circuit, early in the design cycle, so that all iterations on the electrical circuit are based on back-annotated results.

The physical design rules for FinFET technologies are much more restrictive than in previous technology generations. Completing an error free layout requires more iterations and takes significantly longer time than in previous process generations. However, the impact on the design process can be minimized by realizing that during initial design phases, layout iterations with strict abidance to all rules are not mandatory to assess parasitic effects on performance, as long as there is a layout-vs-schematic match. Figure 2 shows a layout example of a 12-bit high speed ADC in FinFET processes. 

FinFET layout example: a 12-bit high speed ADC

Figure 2: FinFET layout example: a 12-bit high speed ADC

Metal Stacks and Coloring

Double patterning was a key advantage for FinFET processes as it enabled finer shape pitches with basically the same lithography pitch, both at device levels and at metal routing levels.

For most analog designs, the CAD tools and design rules allow the designer to ignore double patterning because the design tools will automatically color (the process of selecting which of the two pattern/mask is used for each shape) the design. However, in analog designs, there are matching critical structures like Metal-oxide-Metal (MOM) capacitors, or critical signal traces for which matching characteristics could be impacted by uneven selection of colors in otherwise matched layouts. In these cases, the designer can implement balanced coloring to ensure best matching. Figure 3 shows an example of MOM capacitors with skewed finger organization because of different design grids per metal layer in advanced processes. For matching purposes, the corresponding finger in each capacitor should be fabricated in the same mask (color).

Figure 3: Example of MOM capacitor layout in FinFET

Figure 3: Example of MOM capacitor layout in FinFET

These considerations are especially relevant for designs that rely on switched capacitor architectures to implement the analog functions, for example analog-to-digital converters. Similar considerations apply to circuits where accurate matching between current sources is key to device performance, for example in a current or voltage steering DAC.

High-density routing, a side-effect of the reduced pitch, is the resistivity of metal traces, and substantially increases side-wall parasitic capacitance. In some analog designs, self-induced noise in critical paths or supplies and total load (including parasitic) on critical nodes can severely impact circuit performance. In some cases, it can completely eliminate the speed benefits of more advanced processes, impacting the performance as well as power dissipation of the system. Side effects must be evaluated very early and simulations based on (RCC) layout extraction are mandatory in every design phase.


The successful development of data converters and other Analog IP blocks in FinFET technologies forces designers to deploy optimized design methodologies to take full advantage of the processes’ high speed, low power and area. Proven methodologies in planar CMOS designs in 28-nm are no longer usable as they lead to exceedingly slow design cycles with too many design iterations and ultimately deficient performance and yield. Synopsys’ DesignWare Data Converters IP portfolio supports designs migrating from planar CMOS to FinFET technologies. The IP portfolio enables designers to meet analog front-end interface requirements, while lowering bill-of-materials cost and minimizing integration constraints such as routing and bump placement. The SAR-based architecture for the 12-bit high-speed DesignWare ADCs deliver up to 320 MSPS data rates and offers parallel assembly options for improved area, lower power and architectural scalability. The 12-bit DACs provide low power at rates up to 640 MSPS for high signal bandwidth. Synopsys’ broad portfolio of data converter IP has been integrated in more than 300 system-on-chips (SoCs) across a wide range of processes, and enables designers to lower integration risk and speed time-to-market.