The semiconductor industry continues to evolve to meet user demands for more features, performance, and battery life for less cost in each new generation of products for applications like mobile devices and digital homes. The evolution of the semiconductor process technology as captured by Moore’s law is the key enabler of such products. An important milestone for the industry was the transition from processes based on bulk, planar transistors to FinFET, tri-dimensional transistors. The transition enabled process technologies to continue to evolve for several more generations and deliver reduced feature size, high speed and low leakage.
Traditionally, the first products that are deployed in advanced process technologies implement overwhelmingly digital-centric data processing, whereas analog processing is kept in more conservative process technologies. Designers choose to leverage the more analog-friendly characteristics of the conservative processes, and mistakenly perceive that analog block area does not scale in advanced process technologies or can become expensive.
The evolution of technologies such as wireless connectivity with more than 10 Gbps data throughput per connection and device connectivity at a massive scale (100 billion links) requires more complex digital signal processing. For this reason, designers should consider the benefits of FinFET technology’s high-performance, low power and small area advantages. If the bulk of the analog functionality is integrated into a separate die, such as a RF chip, then it needs data converters – analog-to-digital (ADC) and digital-to-analog (DAC) – as the interface between the external analog processing functions and the internal digital processing blocks. Such data converters are typically integrated in the digital SoC to eliminate the need for additional power-intensive digital interfaces. Therefore, the need to deploy data converters in FinFET processes becomes paramount. This article describes how designers can overcome the challenges of data converter designs with IP for FinFET processes.