Cloud native EDA tools & pre-optimized hardware platforms
ASIP Designer comes with an extensive library of example processor models provided as nML source code. They can be used as a starting point for architectural exploration and customer-specific production designs, or just be partially leveraged as reference implementation for selected architectural features. All these models come with a fully working toolset, SDK and synthesizable RTL, but are not to be considered as verified IP.
Compact 16-bit RISC microcontroller
Compact 16-bit RISC microcontroller with reduced hardware
Trv (Family)
Variants of microcontrollers with RISC-V ISA
DLX (Family)
Variants of Hennessy & Patterson 32-bit RISC microcontroller DLX
16/32-bit DSP with single MAC unit, dual load-store units with post-modify addressing, and 3-way instruction-level parallelism in 16/32-bit variable-length instructions
Tvec (Family)
Variants of wide SIMD processor, with per-lane predication controlled by either predicate registers or a predicate stack, and gather/scatter-based vector addressing. Additional family member supports compilation of OpenCL C kernels
Tvliw (Family)
Variants of a 4-slot VLIW processor, with predication of VLIW slots and instruction compaction
Tutorial model used in basic processor modeling hands-on laboratory
Historic educational model used in manuals
Video accelerator for motion estimation
Accelerator for gaussian image filtering
SIMD vector processor for communication kernels, supporting complex-type operations
Scalar accelerator for block matrix inversion
Scalar FFT accelerator
Accelerator for 5G New Radio MMSE equalization using Cholesky decomposition
Accelerator for SHA256 hashing by extension of a RISC-V scalar core
AI accelerator for MobileNet Convolutional Neural Network
Primecore *
ASIP for FFT and DFT computation in 4G/5G mobile devices, supporting:
Tcrypt *
Accelerator for AES encryption and decryption
Tvox *
Accelerator for simultaneous localization and mapping (SLAM)
JEMA/JEMB *
Dual-ASIP design for JPEG encoding
* Available on demand. For more information, please contact Synopsys by sending your request to asipinfo@synopsys.com
16-bit microcontroller |
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16-bit microcontroller with reduced hardware (based on Tmicro) |
Differences to Tmicro:
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The Trv family is a collection of RISC-V processor models combining different data path widths, pipeline depths, and optional extensions. The base models, supporting integer and multiplication instructions, are labeled Trv<ww>p<n>[f][x][c], with <ww> denoting the data path width (32 or 64) and <n> denoting the pipeline depth (3 or 5). Optional extensions are indicated by additional suffixes:
A separate model, Trv32p3sdx, with “sdx” denoting “simple data path extensions” contains a low-barrier modeling skeleton for custom data path extensions and comes with a set of example implementations for different application domains, such as FFT, SHA256 encryption, and a neural network for keyword spotting.
The following table lists the features of the available Trv family models in detail.
Trv32p3 (base model): 32-bit RISC-V microcontroller with RVIM32 instruction set
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Trv32p3x (variant): Trv32p3 with DSP extensions |
Features on top of Trv32p3:
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Trv32p3f (variant): Trv32p3 with floating-point hardware support (RVIMF32 instruction set) |
Features on top of Trv32p3:
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Trv32p3fx (variant): Trv32p3f with DSP extensions |
Features on top of Trv32p3f:
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Trv32p3c (variant): Trv32p3 with compressed instruction support (RVIMC32 instruction set) |
Features on top of Trv32p3:
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Trv32p5 (variant): 32-bit RISC-V microcontroller with RVIM32 instruction set and 5-stage pipeline |
Features different from Trv32p3:
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Trv32p5x (variant): Trv32p5 with DSP extensions |
Features on top of Trv32p5:
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Trv32p5f (variant): Trv32p5 with floating-point hardware support (RVIMF32 instruction set) |
Features on top of Trv32p5:
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Trv32p5fx (variant): Trv32p5f with DSP extensions |
Features on top of Trv32p5f:
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Trv64p3 (base model): 64-bit RISC-V microcontroller with RVIM64 instruction set
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Trv64p3x (variant): Trv64p3 with DSP extensions |
Features on top of Trv64p3:
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Trv64p5 (variant): 64-bit RISC-V microcontroller with RVIM64 instruction set and 5-stage pipeline |
Features different from Trv64p3:
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Trv64p5x (variant): Trv64p5 with DSP extensions |
Features on top of Trv64p5:
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Trv32p3sdx (variant): Trv32p3c with skeleton for custom data path extensions |
Features on top of Trv32p3c:
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DLX (base model): 32-bit microcontroller (Hennessy & Patterson DLX)
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FLX (variant): DLX with HW floating point unit |
Features on top of DLX base model:
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TLX (variant): DLX with reduced register file and exposed shallower pipeline |
Features different from DLX base model:
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ILX (variant): DLX with multi-threading support, exposed pipeline |
Features different from DLX base model:
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PLX (variant): DLX with multi-threading support, protected pipeline |
Features different from DLX base model:
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VLX (variant): DLX with SIMD vector extensions |
Features on top of DLX base model:
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BLX (variant): DLX with simple branch predictor |
Features on top of DLX base model:
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16/32-bit DSP with single MAC unit, dual load-store units with post-modify addressing, and 3-way instruction-level parallelism in 16/32-bit variable-length instructions |
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Tvec1 (base model): Scalar microcontroller with additional SIMD vector data path |
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Tvec2 (variant): Tvec1 with vector predication |
Features on top of Tvec1:
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Tvec3 (variant): Tvec1 with condition vector stack |
Features on top of Tvec1:
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Tvec4 (variant): Tvec2 with lane-based vector addressing |
Features on top of Tvec2:
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Tvec5 (variant): Tvec3 with scalar-based vector addressing |
Features on top of Tvec3:
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Tvec6 (variant): Tvec2 with scalar-based vector addressing and support for multiple vector types on shared vector ALU |
Features on top of Tvec2:
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Tvliw1 (base model): 32-bit microprocessor with 4-slot VLIW instruction level parallelism |
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Tvliw2 (variant): Tvliw1 with variable-length instruction level parallelism |
Features on top of Tvliw1:
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Tvliw3 (variant): Tvliw2 with additional 2-cycle program fetch pipeline |
Features on top of Tvliw2:
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Tutorial model used in basic processor modeling hands-on laboratory |
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Historic educational model used in manuals |
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Video accelerator for motion estimation |
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Accelerator for Gaussian image filtering |
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SIMD vector processor for communication kernels, supporting complex-type operations |
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Scalar accelerator for block matrix inversion |
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Scalar FFT accelerator (minimal core optimized for FFT application kernel, without support for C built-in types or arbitrary C code) |
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Accelerator for 5G New Radio MMSE equalization using Cholesky decomposition, with FLX processor as scalar base | Features on top of FLX:
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Accelerator for SHA256 hashing by extension of a RISC-V scalar core |
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AI accelerator for MobileNet Convolutional Neural Network, with Trv32p3 RISC-V processor (RV32IM ISA) as scalar base | Features on top of Trv32p3:
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