ASIP Models

16-bit microcontroller

• 16-bit integer data path
• 3-stage exposed pipeline
• 8x16-bit general-purpose register file
• 16-bit instruction width
• 32-bit multi-cycle multi-word long immediate instructions
• Single data memory
• Separate AGU with indirect addressing and post-modify addressing modes
• Additional features:
  • 16x16->32-bit multiplier
  • 16-bit serial divider
  • Zero-overhead loop support:
    • 3-level do-loop
  • Interrupt support
  • OCD support

16-bit microcontroller with reduced hardware (based on Tmicro)

• No HW multiplier
• No serial divider
• No separate AGU: address computations are performed on the ALU
• No zero-overhead loop support
• No 32-bit instructions

Trv32p3 (base model):

32-bit RISC-V microcontroller with with 3-stage pipeline

• Supported ISA:
  • RV32IM: base integer instructions + multiplication + division
  • Zicsr: control and status register instructions
  • Zba: advanced address generation
  • Zbb: basic bit manipulation
  • Zbs: single-bit instructions
• 32-bit integer data path
• 3-stage protected pipeline
  • Bypasses & HW stalls
• 32x32-bit general-purpose register file
• 32-bit instruction width
• Single data memory
• Separate AGU with indirect addressing
• Additional features:
  • 32x32->64-bit multiplier
  • 32-bit serial divider
  • Interrupt support
  • OCD support

Trv32p3x (variant):

Trv32p3 with DSP extensions

Features on top of Trv32p3:

• 2-way static ILP:
  • arith/ctrl || move/load/store
• Zero-overhead loop support:
  • 2-level do-loop
  • 1-level zloop
• AGU with post-modify addressing modes

Trv32p3f (variant):

Trv32p3 with floating-point hardware support

Features on top of Trv32p3:

• Supported ISA:
  • RV32IMFZfinx
• FPU based on HardFloat [Hauser]
• Single-precision serial division & square-root unit

Trv32p3fx (variant):

Trv32p3f with DSP extensions

Features on top of Trv32p3f:

• 2-way static ILP:
  • arith/ctrl || move/load/store
• Zero-overhead loop support:
  • 2-level do-loop
  • 1-level zloop
• AGU with post-modify addressing modes

Trv32p3c (variant):

Trv32p3 with compressed instruction support

Features on top of/different from Trv32p3:

• Supported ISA:
  • RVC: Support for 16-bit compressed instruction format
• No interrupt support

Trv32p5 (variant):

32-bit RISC-V microcontroller with 5-stage pipeline

Features different from Trv32p3:

• 5-stage protected pipeline (instead of 3)

Trv32p5x (variant):

Trv32p5 with DSP extensions

Features on top of Trv32p5:

• 2-way static ILP:
  • arith/ctrl || move/load/store
• Zero-overhead loop support:
  • 2-level do-loop
  • 1-level zloop
• AGU with post-modify addressing modes

Trv32p5f (variant):

Trv32p5 with floating-point hardware support

Features on top of Trv32p5:

• Supported ISA:
  • RV32IMFZfinx
• FPU based on HardFloat [Hauser]
  
• Single-precision serial division & square-root unit

Trv32p5fx (variant):

Trv32p5f with DSP extensions

Features on top of Trv32p5f:

• 2-way static ILP:
  • arith/ctrl || move/load/store
• Zero-overhead loop support:
  • 2-level do-loop
  • 1-level zloop
• AGU with post-modify addressing modes

Trv64p3 (base model):

64-bit RISC-V microcontroller with 3-stage pipeline

• Supported ISA:
  • RV64IM: base integer instructions + multiplication + division
• 64-bit integer data path
• 3-stage protected pipeline
  • Bypasses & HW stalls
• 32x64-bit general-purpose register file
• 32-bit instruction width
• Single data memory
• Separate AGU with indirect addressing
• Additional features:
  • 64x64->128-bit multiplier
  • 64-bit serial divider
  • OCD support

Trv64p3x (variant):

Trv64p3 with DSP extensions

Features on top of Trv64p3:

• 2-way static ILP:
  • arith/ctrl || move/load/store
• Zero-overhead loop support:
  • 2-level do-loop
  • 1-level zloop
• AGU with post-modify addressing modes

Trv64p5 (variant):

64-bit RISC-V microcontroller with 5-stage pipeline

Features different from Trv64p3:

• 5-stage protected pipeline (instead of 3)

Trv64p5x (variant):

Trv64p5 with DSP extensions

Features on top of Trv64p5:

• 2-way static ILP:
  • arith/ctrl || move/load/store
• Zero-overhead loop support:
  • 2-level do-loop
  • 1-level zloop
• AGU with post-modify addressing modes

Trv32p3sdx (variant):

Trv32p3c with skeleton for custom data path extensions

Features on top of Trv32p3c:

• Model stubs for low-barrier modeling of extension instructions
• Shared 32x32-bit / 16x64-bit register file to enable both 32-bit and 64-bit extensions
• Zero-overhead loop support:
  • 2-level do-loop
• AGU with post-modify addressing modes

DLX (base model):

32-bit microcontroller (Hennessy & Patterson DLX)

• 32-bit integer data path
• 5-stage protected pipeline
  • Bypasses & HW stalls
• 32x32-bit general-purpose register file
• 32-bit instruction width
• Single data memory
• Separate AGU with indirect addressing and post-modify addressing modes
• Additional features:
  • 32x32->32-bit multiplier
  • 32-bit serial divider
  • Zero-overhead loop support:
    • 2-level do-loop
    • 1-level zloop
• Interrupt support
• OCD support

FLX (variant):

DLX with HW floating point unit

Features on top of DLX base model:

• 32-bit floating-point unit
• Floating-point multicycle divider and square-root
• Variant with custom 24-bit non-IEEE floating-point type

TLX (variant):

DLX with reduced register file and exposed shallower pipeline

Features different from DLX base model:

• Reduced register file (16 x 32-bit)
• 3-stage exposed pipeline

MLX (variant):

DLX with two-stage fetch pipeline

Features different from DLX base model:

• Two-cycle latency for PM loads, resulting in a two-stage fetch pipeline

ILX (variant):

DLX with multi-threading support, exposed pipeline

Features different from DLX base model:

• 4-way static multi-threading support
• 4-fold instantiation of original DLX register set
• 5-stage exposed pipeline

PLX (variant):

DLX with multi-threading support, protected pipeline

Features different from DLX base model:

• 8-way static multi-threading support
• 8-fold instantiation of original DLX register set

VLX (variant):

DLX with SIMD vector extensions

Features on top of DLX base model:

• 4-lane SIMD vector ALU (4 x 32-bit)
• 16 x 128-bit vector register file
• Vector load/store (128-bit memory access)
• 5-stage protected vector pipeline:
  • Bypassed vector registers

BLX (variant):

DLX with simple branch predictor

Features on top of DLX base model:

• Branch prediction logic
• Branch target buffer (BTB) with 64 entries, fully associative content-addressable memory

16/32-bit DSP with single MAC unit, dual load-store units with post-modify addressing, and 3-way instruction-level parallelism in 16/32-bit variable-length instructions

• 16/32-bit fractional data path
• 3-stage exposed pipeline
  • Bypassed modifier registers only
• Register files:
  • 8x16-bit data register file
  • 4x32-bit long-word register file
  • 8x20-bit pointer register file
  • 4x16-bit modifier register file
• 16/32-bit instructions
• Dual-port data memory
• 2 AGUs with post-modify and cyclic addressing modes
• Additional features:
  • 16x16->32-bit MAC unit
  • 32-bit serial divider
  • Zero-overhead loop support:
    • 3-level do-loop
  • Interrupt support
  • OCD support

Tvec1 (base model):

Scalar microcontroller with additional SIMD vector data path

• Based on Tmicro
• 16-bit integer scalar data path
• 128-bit SIMD vector data path
• 3-stage exposed pipeline
• Register files:
  • 8x16-bit scalar register file
  • 4x128-bit vector register file
• 16-bit instruction width
• Single data memory with support for both scalar and wide vector access
• Single AGU with indirect and post-modify addressing modes
• 8-lane SIMD vector ALU
  • (additive arithmetic, logic, min/max, vector sum)
• Additional features:
  • 16x16->32-bit scalar Multiplier/mac unit
  • No hardware divider
  • Zero-overhead loop support:
    • 3-level do-loop
  • Interrupt support
  • OCD support

Tvec2 (variant):

Tvec1 with vector predication

Features on top of Tvec1:

• 4x8-bit vector condition register file
• Guarded SIMD instructions via vector predication (lane-enables)

Tvec3 (variant):

Tvec2 with vector-based vector addressing

Features on top of Tvec2:

• Vector load/store instructions with vector-based vector addressing

Tvec4 (variant):

Tvec2 with scalar-based vector addressing

Features on top of Tvec2:

• Vector load/store instructions with scalar-based vector addressing
• Gather-scatter I/O interface to resolve memory bank access conflicts

Tvec5 (variant):

Tvec4 support for multiple vector types on shared vector ALU

Features on top of Tvec4:

• Vector ALU supporting two vector types on shared hardware:
  • 8x16-bit SIMD data path
  • 4x32-bit SIMD data path

Tvliw1 (base model):

32-bit microprocessor with 4-slot VLIW instruction level parallelism

• 32-bit integer data path
• 3-stage exposed pipeline
• Register files:
  • 16x32-bit data register file
  • 8x32-bit pointer register file
  • 8x32-bit modifier register file
• 96-bit instruction width
• 4-way VLIW instruction level parallelism
  • 2 arithmetic slots
  • 2 load/store/move slots
• Dual-port data memory
• 2 AGUs with post-modify addressing modes
• Additional features:
  • 32x32->32-bit multiplier
  • Zero-overhead loop support:
    • 1-level do-loop

Tvliw2 (variant):

Tvliw1 with variable-length instruction level parallelism

Features on top of Tvliw1:

• Variable-length instruction formats with predecoding and expansion in the PCU:
  • 1 to 4 parallel instructions
  • 24/48/72/96-bit instruction width
• Instruction predication based on up to 8 dynamic conditions
• 8x1-bit condition register file for instruction predication

Tvliw3 (variant):

Tvliw2 with additional 2-cycle program fetch pipeline

Features on top of Tvliw2:

• Program fetch pipeline supporting program memory with 2-cycle load latency
• Loop instruction buffer

Tutorial model used in basic processor modeling hands-on laboratory

• 16-bit integer data path
• 4-stage exposed pipeline
• 8x16-bit register file
• 16-bit ALU
• 14-bit instruction width
• Single-port memory with indirect and post-increment addressing modes
• No separate AGU, address computation performed on ALU
• Zero-overhead loop support:
  • 1-level do-loop

Historic educational model used in manuals

• 16-bit integer data path
• 4-stage exposed pipeline
• Register files:
  • 8x16-bit distributed data register file
  • 4x10-bit distributed pointer register file
  • 4x10-bit distributed modifier register file
• 18-bit instruction width
• Dual-port data memory
• 2 AGUs with post modify addressing modes and separated pointer/modifier register subsets
• 16-bit ALU with dedicated operand/result registers
• Additional features:
  • 16x16->32-bit scalar multiplier/mac unit with dedicated operand/result registers
  • Zero-overhead loop support:
    • 1-level do-loop

Video accelerator for motion estimation

• Based on Tmicro
• 8/16-bit scalar data path
• 128-bit SIMD vector data path
• 3-stage exposed pipeline
• Register files:
  • 8x16-bit scalar register file
  • 4x128-bit vector register file
• 16/32/48-bit instructions
• Shared scalar/vector data memory with unaligned 128-bit vector access
• Dedicated coefficient memory with 128-bit vector access
• 2 AGUs with post-modify addressing modes
• 16-lane SIMD vector ALU with specialized vector absolute-difference instructions
• Zero-overhead loop support:
  • 3-level do-loop

Accelerator for Gaussian image filtering

• Based on TLX
• 16/32-bit scalar data path
• 48-bit SIMD vector data path
• 4-stage exposed pipeline
• Register files:
  • 16x32-bit scalar register file, split into separately accessible 16-bit low/high parts
  • Two distributed 10x48-bit vector register files with cyclic buffer access
  • 16x5-bit pointer register file for cyclic buffering
• 32-bit instructions
• 32-bit scalar data memory
• Separate vector memories for the input/output image
• Separate vector memory for line buffers
• 2x24-bit vector data path (2 RGB pixels) with 6-lane bytewise multiply/accumulate unit
• Additional features:
  • 32x32->32-bit pipelined multiplier (2 cycles)
  • 32-bit sequential divider performing 3 iterations in parallel
  • Zero-overhead loop support:
    • 3-level do-loop
  • OCD support

SIMD vector processor for communication kernels, supporting complex-type operations

• Based on Tmicro
• 16/32-bit scalar data path
• 128-bit SIMD vector data path
• 4-stage exposed pipeline
• Register files:
  • 8x16-bit scalar register file,
  • 4x128-bit vector register file
  • 4x320-bit partitioned vector accumulator register file
  • 4x16-bit pointer register file
  • 4x16-bit modifier register file
• 32-bit instruction width
• 2-way static ILP for scalar/vector instructions
• 4-way static ILP for custom FFT instructions
• Dual-port vector memory and separate single-port vector coefficient memory
• 3 AGUs supporting cyclic, bit-reverse and specialized next-butterfly addressing modes
• 8x40-bit/4x80-bit shared vector ALU supporting 8-lane SIMD fixed-point or 4-lane SIMD complex-fixed-point operations:
  • Vector shift unit
  • Vector multiply/MAC
  • Vector butterfly (complex only)
• Additional features:
  • 16x16->32-bit multiplier
  • 16-bit serial divider
  • Zero-overhead loop support:
    • 3-level do-loop
  • Interrupt support
  • OCD support

Scalar accelerator for block matrix inversion

• 32-bit integer/floating point data path with 2x32-bit complex number support
• 3-stage exposed pipeline
• Register files:
  • 8x32-bit data register file,
  • 4x16-bit pointer register file
  • 4x16-bit modifier register file
• 16/32-bit instruction width
• 2-way static ILP
  (arithmetic || memory/move/control)
• Single AGU with post-modify addressing modes
• 32-bit integer ALU
• 32-bit floating-point ALU
• Additional features:
  • 32x32->64-bit integer multiplier
  • 32-bit floating point multiplier
  • 32-bit sequential divider (int and float) performing 3 iterations in parallel
  • Zero-overhead loop support:
    • 2-level do-loop
  • OCD support

Scalar FFT accelerator

(minimal core optimized for FFT application kernel, without support for C built-in types or arbitrary C code)

• 48-bit complex fixed-point data path
• 3-stage exposed pipeline
• Two distributed register files of 4x48-bit each
• 20-bit instruction width
• Up to 5-way ILP for FFT inner loop
  • (load || store || coef_load || mul || butterfly)
• 2 data memories, 1 separate coefficient memory
• 3 specialized AGUs with post-modify, circular, and custom butterfly addressing modes
• 48-bit ALU with complex multiply and butterfly
• Zero-overhead loop support:
  • 2-level do-loop

Features on top of FLX:

• 64-bit complex floating-point data path
• N-lane SIMD complex vector processing unit with design-time configurable vector size / number of lanes using N as parameter
• 8 x (Nx64-bit) vector register file
• 64-bit instruction width
• 4-way ILP:
  • (scalar/memory || move || vector complex mul || vector complex add/sum)
• Vector load/store with various application-specific post modify addressing modes tuned for efficient access of matrix elements during Cholesky decomposition
• Balanced data path to maximize memory bandwidth utilization

Accelerator for 5G Low Density Parity Check decoding, by extension of a RISC-V scalar core (Trv32p5x)

Features on top of Trv32p5x:

• 128-lane SIMD vector processing unit (128 x 8-bit) with specialized instructions for variable rotation, addsub, minimum detection and element selection
• 8 x 1024-bit vector register file
• 64-bit instruction width
• Up to 4-way ILP:
  • Split arith/ctrl and move/ldst slots of original Trv32p5x to support scalar ldst || vector ldst || dual vector arith
• Dedicated 1024-bit wide vector memory

Accelerator for SHA256 hashing by extension of a RISC-V scalar core

• Based on Trv32p3 (RV32IM ISA), reduced by unused features:
  • No hardware multiplier
  • No hardware divider
  • No OCD support
  • Reduced register file (see below)
• 3-stage protected pipeline:
  • Bypasses & HW stalls
• 16x32-bit register file
• Dedicated SHA256-step instructions
• Separate data memory for K-table
• 2 AGUs with post-modify addressing modes
• 32-bit instruction width
•  3-way ILP for critical loop instructions:
  • (SHA-step || load data || load K-table)
• Zero-overhead loop support:
  • 1-level zloop

Accelerator for the Kyber key encapsulation mechanism (post-quantum cryptography) by extension of a RISC-V scalar core (Trv32p5x)

Features on top of Trv32p5x:

• Support for SHA3 hashing
  • 25x64-bit dedicated state register file
  • 64-bit load/store instructions
  • Keccak hash unit with dedicated instruction
• Dedicated instructions for Kyber modulo-based operations
  • 2-way packed SIMD
  • Montgomery and Barret reduction
  • NTT butterfly

Features on top of Trv32p3:

• Additional, 4^th pipeline stage used for vector memory load only
• 64-lane SIMD vector processing unit (64x8-bit data path)
  • Including 64-lane vector mac unit (8x8->32-bits)
• Many distributed register files, including:
  • 4x64-bit vector register file
  • 3x512-bit matrix register file
  • 3x2048-bit vector accumulator register file
• Separate vector memories:
  • Vector feature memory with vector addressing
  • Vector weight memory with scalar addressing
• 90-bit instruction width
• 4-way ILP:
  • (scalar || vector arithmetic || vector feature memory || vector weight memory)
• Zero-overhead loop support:
  • o   3-level do-loop
  • o   1-level zloop