How to Integrate USB4 in Your Next SoC Design

Morten Christiansen

Apr 06, 2022 / 6 min read

For many users worldwide, the advent of USB Type-C has unveiled a whole new level of convenience and simplicity to everyday life. USB4 enables enhanced compatibility using a single connector and cable providing data, video, and power with a superior transfer speed of up to 40 gigabits per second (Gbps). USB provides improved display and fair bandwidth allocation, changing the way we connect and use our computers and peripherals like display, storage, audio and video input devices, etc.

First created in the early 1990s, USB 1.0 was designed to standardize how devices such as printers, keyboards, and mice connected to a personal computer using 1.5 megabits per second (Mbps) or 12 Mbps connections. Since then, the implementation of USB technology has changed drastically, from supporting significantly higher data rates to better compatibility and universal adoption. USB4 is the next evolutionary step that enables efficient and effortless connections, use, and charging of all our devices.

For designers, USB4 means greater complexity. Ensuring that chip designs meet the latest standard specifications will be essential as the market comes to expect the benefits that the latest versions offer. From the consumer’s perspective, USB4 connectivity means that a single cable provides not just data, but also video and power with convergence of protocols. This means that the “portable office in your pocket” via a USB4-enabled smartphone, tablet, or 2-in-1 is just around the corner or already here in some cases. Whether you’re scanning a document from your office scanner, connecting to the office work desk, or connecting two 4K displays for your multi-monitor work-from-home setup, a single USB4-enabled cable is all you need to make that connection.

The key USB peripheral that we see moving to USB4 is mass storage devices that can run at up to twice the speed of USB 3.2 when connected to a USB4 capable host. Additionally, backwards compatibility means these storage devices will work with any host, regardless of host capability. We also expect to see artificial intelligence (AI) edge devices that will function as a compute stick augmenting AI capability move to USB4. USB4 enables easier integration with various hosts, allowing developers to easily debug these new edge AI applications and deploy them in the field. Consumers will rightly expect USB products to be fully compatible with any host and support the multiple operating modes that exist now and that will be developed in the future.

Read on to learn more about how USB4 differs from USB 3.2, the attributes of the USB4 host, hub, dock, and device, and how the latest Synopsys USB4 IP can help designers reduce the challenges of greater complexity.

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USB4 vs USB 3.2: Two Different Species

While USB4 uses the same Type-C connector as USB 3.2, USB4 is far more complex. USB4 allows simultaneous host-to-host, PCI Express® (PCIe®), DisplayPort audio/video, and USB data on the same link and USB Type-C connector. This convergence enables exciting new developments such as the portable office outlined above.

Host-to-host tunneling makes it possible to exchange IP packets between two USB4 hosts; DisplayPort and USB tunneling means audio, video, data, and power can travel on the same connector, faster than with USB 3.2. In addition, PCIe tunneling provides higher bandwidth and lower latency, enabling high-throughput mass storage, edge AI, and multiple other use cases.

USB4 20 Gbps and 40 Gbps rates are achieved by bonding the two transmission (TX) and receiving (RX) lanes on the USB-C connector. Each lane uses the “rounded” 10 Gbps or 20 Gbps data rate. While this isn’t a feature that users need to know, designers need to be aware that Thunderbolt3 mode uses a 10.3125 Gbps or 20.625 Gbps data rate per TX and RX lane. When in Legacy USB mode, one or the other TX/RX lane runs at 5Gbps for USB 3.0 or 10Gbps for USB 3.1. For USB 3.2, both lanes run at 10Gbps.

A Multitude of SoC Design Considerations

For chip designers, the goal remains the same as always in the context of USB: to provide products that from a user perspective “just work.” To integrate USB4 into the next system-on-a-chip (SoC) design, the first step is to acknowledge the complexity of the published USB4 specification. Designers also need to understand USB 3.2, USB 2.0, USB Type-C, and USB Power Delivery, as well as PCIe, DisplayPort, and High-Definition Content Protection (HDCP) specifications.

Designing USB4 products calls for a range of building blocks which Synopsys offers, spanning host, hub, dock, and device. Let’s take a look at the basic architecture of these components:

  • USB4 Hosts have a host interface, DisplayPort Source, and Enhanced SuperSpeed USB host controller that connect to the host router in USB4 mode. A PCIe Root Complex Controller is optional according to the USB4 specification, but all current USB4 Host implementations include support for tunneled PCIe. USB4 Hosts must also support legacy USB and DisplayPort Alternate Mode. This ensures backwards compatibility with existing USB and DP Alt Mode peripherals.
  • USB4 Hubs, meanwhile, have one upstream-facing port (UFP) and one or more downstream-facing ports (DFPs) according to the USB4 specification: having a single UFP helps mitigate complexity from a design perspective and confusion from a user one. Note that a USB4 hub is far more complex than its USB 3.2 or USB 2.0 counterparts, as it incorporates both legacy USB hubs, as well as a PCIe switch and the USB4 device router.
  • The USB4 Dock also has one UFP and one or more DFPs. The difference between hub and dock is that USB4 Dock also has integrated functions such as an Ethernet adapter, USB audio function, DisplayPort output connection to the legacy DisplayPort, and legacy connectors for USB keyboard, mouse, storage, camera, and so forth.
  • The USB4 Device is the simplest USB4 product. It has one USB4 UFP and no USB4 DFP. As such, it represents the end point of the USB4 system because no additional USB4 hubs, docks, or devices can connect to it. The more functionality it requires, however, the more complex it inevitably becomes.
USB4 Specification | Synopsys

Bringing USB4-Enabled Designs to Market Faster

To put things into perspective, the IEEE Bandwidth Assessment Report from April 2020 projected the number of internet users and devices in 2022 against that of 2017. Five years ago, there were 3.4 billion internet users; today, that number has swelled to 4.8 billion. With the increase in users, the number of device connections has also risen from 18 billion to 28.5 billion, with average monthly gigabyte consumption per user up from 29% to 85%.

With the rapid increase in the amount of data generated and transmitted (intensified by the ongoing COVID-19 pandemic and increased amounts of remote learning and working), today’s applications demand faster data network and device interface speeds. The need to effortlessly change between the new work-at-home and the older office environment is enabled by USB4.

It has become more challenging for designers to ensure all components of a system work together. Synopsys introduced the industry’s first complete USB4 solution, Synopsys DesignWare® USB4 IP. The aim is simple: to ensure USB4 designs meet or exceed user expectations and speed up their time to market.

The DesignWare USB4 IP solution supports all applications under the USB4 specification with physical layer (PHY), router, controller, and verification IP. The first USB4 Hosts will benefit from the latest advanced process nodes. Synopsys provides support for 5nm and 6nm processes and plans to support 12nm process nodes for more mainstream designs when USB4 moves into its next generation — the full spectrum of USB4 peripherals.

The benefits of accelerated data transfer rate, backwards compatibility, flexibility, usability, and the scope of innovation that USB4 enables are truly exciting. While the system’s complexity might at first appear daunting, with the right tools, USB4 functionality is set to quickly become an integral part of an advanced SoC or peripheral ASIC design process.

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