Last month, we announced the silicon proof of DesignWare® 112G Ethernet PHY IP in the 5nm FinFET process, delivering significant performance, power, and area advantages. The 112G Ethernet PHY enables true long-reach channels for up to 800G hyperscale data centers, networking, and AI SoCs.
Keeping in mind the Holy Grail of power, performance, and area (PPA), DesignWare 112G Ethernet PHY in 5nm:
- Enables designers to optimize highly dense SoCs with placement-aware IP that maximizes bandwidth per die-edge through stacking and placement on all four edges of the die
- Demonstrates zero bit-error rate post forward-error correction in greater than 40dB channels while offering power efficiency of less than five picojoules per bit (pJ/bit)
- Supports the Pulse-Amplitude Modulation 4-Level (PAM-4), Non-Return-to-Zero (NRZ) signaling, and independent, per-lane data rates for ultimate flexibility to address a broad range of protocols and applications
Since every customer has unique requirements, Synopsys develops IP that is very flexible and can handle supporting different metal stacks, bump structures that necessitate unique placement requirements, and more. When it comes to logical integration of synthesis review, layout review, timing reviews, package design, power network design, etc., we work with you every step of the way with design checklists and reference designs based on past experiences to make sure no mistakes are made along the way.
At the end of the day, designers need reliable interface IP that can support different Ethernet electrical interfaces in a single PHY and is verified and licensed from a single IP vendor, to keep up with the rising data rates and increased bandwidth demand. This combination provides the flexibility, ROI, and short time-to-market windows that are crucial in today’s competitive landscape.