Broadest Portfolio of SystemC Transaction-level Models
Getting to Market Faster with Models
Today's system-on-chip (SoC) designers are dealing with two increasing pressures: developing highly complex products and getting them to market in a minimum amount of time. To meet these design goals, designers are using larger amounts of Intellectual Property (IP), allowing more time to focus on the unique value and differentiation of their product.
At the same time designers need to have simulation models of all this IP in order to make the best choices about what IP to include in their product. Models should be high quality with fast performance. They also need to provide ways to ease design tasks, such as debug, and the ability to analyze performance problems.
The models in the SystemC TLM Library have been developed in partnership with major IP providers, including market leaders ARM, MIPS, Tensilica, CEVA and Synopsys, giving the designer access to IP vendor reference models and ensuring correct behavior. These models are typical of the IP needed by designers to build platforms, debug hardware and software and verify the design before moving to the RTL implementation flow.
Embedded Processor Models
Embedded Processor Models use Instruction Set Simulators (ISS) to emulate the behavior of the implementation model. By being an abstract representation of the RTL, the simulation performance gained is typically several orders of magnitude faster than the implementation model. This allows hardware and software designers to run more application code or more comprehensive verification suites to prove the design.
Synopsys works with the designer's IP partners, using ISS models certified by the partner, ensuring that the models have the correct functionality and behavior available for SystemC simulation. Based on many years of experience, Synopsys also works with many IP Partners to help them more efficiently create their own SystemC compatible processor models that support features such as virtual memory, debugging and analysis. These models provide maximum value for the Synopsys Architecture Design and Virtual Prototyping solutions.
With the ASIP Designer tool, Synopsys not only offers a unique tool enabling customers to create dedicated and highly optimized custom processors (see Custom Processor Models below), the tool also eases and optimizes the creation of ultra fast instruction accurate processor models. Combined with Synopsys' TLM methodology and the Virtual Prototyping solution, these ultra fast processor models enable early software development.
Synopsys' TLM modeling methodology based on the SystemC TLM Library (SCML) enables reuse of peripherals for multiple design tasks and different communication protocols. These peripheral models can both be used for high-speed software development, hardware-software co design and architectural exploration in combination with the transactors delivered with the Architecture Design Models.
Using this modeling methodology Synopsys delivers functionally accurate SystemC models for the ARM® PrimeCell® family, and the Synopsys DesignWare Interface IP. These models allow the designer to create and configure platforms and develop software early in the development process. On top of that Synopsys delivers a generic IP Library with its tools. This generic IP Library consists of a base set of peripherals that are typically used in any platform.
Custom Processor Models
Synopsys' ASIP Designer allows semiconductor IP vendors or end users to rapidly create models of their processors. This includes standard RISC, DSP and Application-Specific Instruction-set Processor (ASIP) architectures.
ASIP Designer automatically creates the Instruction Set Simulator (at both instruction accurate and cycle-accurate levels), from the nML description language. All necessary software tools are generated, including compiler, assembler, disassembler, linker, profiler and debugger.
Models are continuously added to these libraries. Please contact us for information about availability for specific models.