VC AutoTestbench

Automated Testbench Generation

Synopsys’ VC AutoTestbench automates the generation of testbenches from IP to SoC, enabling system architects and integrators to run system-level tests much earlier in the project schedule. The ‘time to first test’ which often is in the order of days to weeks depending on design complexity is reduced to less than an hour with VC AutoTestbench.

Starting from an IP-XACT description of the design and testbench VIP components, VC AutoTestbench enables quick and easy import, selection, configuration and connectivity of the design under test (DUT) and the corresponding VIP. With the click of a button, the testbench is automatically generated, validated and ready for verification. VC AutoTestbench generates reusable SystemVerilog/UVM testbenches for IP, interconnect and SoC verification.

VC AutoTestbench block diagram