Today's highly complex SoCs typically include multiple application-specific embedded processors, a memory subsystem, multiple interfaces to standard and custom protocols and a sophisticated interconnect architecture. Designs often come together later in the project schedule in a myriad of system configurations. Current SoC-level testbenches don't scale well from the block- to SoC-level, are effort-intensive and time-consuming to build, and inherently error-prone. Hence, there is a pressing need for automation in the overall SoC verification process — starting with the need to automate SoC testbench generation.
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